Cadence ahdlLib: which model to use ahdl or veriloga?

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borodenkov

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ahdl and veriloga

In the ahdlLib in Cadence there are "ahdl" and "veriloga" views. The synthax is different.

I am confused with the difference between them. "veriloga" should be a Verilog-A model. It seems that "ahdl" stands for SpectreHDL language - what is it?

Which model is better to use?
 

Re: ahdl and veriloga

As far as I know, ahdl is phasing out. Verilog-A is the one to use. Verilog-A is the analog subset of emerging language Verilog-AMS.
 

Re: ahdl and veriloga

Also, ahdl may be replaced by VHDL-AMS.
 

Re: ahdl and veriloga

geconom said:
Also, ahdl may be replaced by VHDL-AMS.
Click to expand...

I do not think they are similar. I looked more careful at Cadence docs, "ahdl" is SpectreHDL, Cadence analog simulation language with syntax very close to Verilog-A.
 

ahdl and veriloga

I know AHDL only as Altera HDL for digital designs. The nomenclature is a little bit confusing.
 

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