freewing
Member level 1
I use Cadence Analog Design Environment to simulate a mixed-signal system (Verilog, verilog-A, schematic, spectre models). But there is sth wrong in the interface between a verilog block and voltage source. The voltage source is a sine wave. I did set up a2d IE on the terminals of the verilog block. But this sine voltage source is not correctly converted to digital sequences. The weird thing is when I change it to a pulse voltage source (vpulse), it works well. What could be the reason? Thx.