Cadence ADE Mixed-Signal simulation problem

[freewing]

I use Cadence Analog Design Environment to simulate a mixed-signal system (Verilog, verilog-A, schematic, spectre models). But there is sth wrong in the interface between a verilog block and voltage source. The voltage source is a sine wave. I did set up a2d IE on the terminals of the verilog block. But this sine voltage source is not correctly converted to digital sequences. The weird thing is when I change it to a pulse voltage source (vpulse), it works well. What could be the reason? Thx.

 

[eng_Semi]

If u r declaring a variable, in ur code, to hold the input signal, be sure that u declare it as real not integer.

If the problem exists, send to me the code (if u want)

 

[uncle_urfi]

You have to press 'Q' for querying the a2d, I assume it is coming out of the ahdlLib and then setup the parameters correctly. especially the reference voltage.

With the pulse source, there are only two states and a very brief rise/fall time, but with a sin, the resolution of the converter will play a part.