Caches L1 & L2 interconnect

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ivlsi

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Hi All,

Could you help me with letting know what signals are running between L1 and L2 caches? I did some search with Google, but did not find anything useful. Can somebody help?

Thank you!
 

Well, I beleived that is the "intelligence" of this system, rarely shared or patent protected.
 

Intel published this info for their Pentium processor, I saw it on the net, but cannot find it now...
I'm attaching the interconnect schema, which I have. Could somebody let to know the meaning of the signals there?
 

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