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Cache and DSP - some questions

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brmadhukar

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Cache

Hi,
I was until now using DSP with no cache support and so was novice in uC knid of programming. Now I am supposed to port the same into DSP with cache. The DSP in question is Blackfin with L1 and L2 memory. The question is can I move program from L2 to L1 using DMA in background while I am using L1 for program execution. I do not want use L1 as cache.
TIA
 

Hi,
If the L1 cache is segmented and if the instruction being executed is in L1 can the other (segment) part of cache (can be configured) be filled in by DMA.
BR
 

Hi,
Can anyone point where I can look for answers for the above questions.
TIA
brmadhukar
 

are there any general reference books for cache programming, non RTOS based designs, RTOS designs, principles which deal with optimization of code and speed.
 

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