C-Based Verification Environment

[paulki]

Hi,
In C-based verification environment (Assume Testbench, Testcases and all environment components like Monitor, Checker, Score-boards all are written in C, DUT is written either Verilog/VHDL) how to create Clock Source? In such a verification environment is there any other difficulties to be faced?
Please answer this question, since I'm not worked in any complete C-based environment. Please ignore this question if at all not relevant.

-Paul

 

[sharanbr]

Hi Paul,

In my experience, I have always seen requirement to use a HDL along with C to create a verification environment. How much you would want to accomplish in C and how much in HDL varies.

In C+Verilog environment, the timing aspects are modeled in verilog and things like dynamic memory allocation, data structure etc are kept in C

The communication between verilog and C is established using PLI.
Always remember that the C is passive in this type of environment and has no notion of time as such. For example, it cannot wait for 10 clock cycles, 10 ns etc.

In this type of environment, remember that a thread that can suspend and resume can never be in C. A typical example is test which calls/triggers many other methods and waits until action is completed. So the test thread has to be in verilog.

Similarly, some people use systemc instead of verilog to model timing.

I have so far not seen an verification environment that completely runs in C. Even in case there are some examples, there will always be under the hood HDL engines that might be transparent to user but will run nevertheless.

There are some techniques to create verification environment completely in C, but the effort required and the limitations these methods impose are too many.

Regards,

 

[ljxpjpjljx]

also you can use system-c model to do the testbench!