[SOLVED] Bypassing Cadence MOSFET Size Limits

[Waddy]

Hello Everyone,

I am using Cadence to simulate some MOSFET behavior using the TSMC 0.18 µm process. I am testing the accuracy of some equations I have derived and need to be able to use very long channel lengths (≈35 µm) to verify the operation (across several regions of inversion). In PSPICE I was able to choose what ever size I needed, but in Cadence I get an error saying I need to use dimensions within the size specified by the model file. I would just change the model file to allow for larger dimensions but it is on a shared network and is not editable. Is there some way that I can deactivate this error and force simulation?

Thanks

 

[erikl]

You can copy the original model to another name and remove the length limitation.
You probably know its reason: this should guarantee a certain analysis accuracy for a certain parameter range.

 

[dick_freebird]

You can copy your whole models directory to

$PROJECT_HOME/models/spectre,

change the permissions and edit as you please, and change
the pointers to use your local models. In the instance
placement popup there may be an "ignore limits" checkbox
(there is in my PDKs, which are not TSMC).

 

[Waddy]

Thanks for all the help! I will check to see if there is an "ignore limits" checkbox for TSMC, if not it looks like I will be copying the models to my personal directory. I will just cross my fingers and hope that everything is still somewhat accurate past the designated limits.

 

[dick_freebird]

Very rarely a problem going bigger, as far as the model
goes. But if you look at things like body tie ("tap"?) rules,
a maximum distance to active implies a maximum gate
area that while simulatable, may fail your layout further
down the line.