library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity motor_demo is
port( clk: in std_logic;
RST, EN, CTRL, HALF, CW, Step_clk: out std_logic;
sw: in std_logic_vector(0 to 4);
sw_check: out std_logic_vector(0 to 4)
);
end motor_demo;
architecture stm of motor_demo is
type motor_action is (STOP, CWISE, CCWISE);
signal motor_state: motor_action := CWISE;
signal stepcount: integer := 0;
signal clk_div: std_logic;
signal drive: std_logic := '0';
signal cw_45, ccw_180: std_logic := '0';
begin
-- Clock divider for stepper action
clk_divider: entity work.clk_divide port map(clk, clk_div);
-- Motor control lines
EN <= '1';
RST <= '1';
CTRL <= '1';
HALF <= '1';
-- switch debugging
sw_check <= sw;
-- driving the step clock
with drive select
step_clk <= clk_div when '1',
'0' when '0',
'0' when others;
process(clk_div, motor_state, sw) is
begin
if rising_edge(clk_div) then
if sw(0) = '0' then
motor_state <= CWISE;
elsif sw(1) = '0' then
motor_state <= CCWISE;
elsif sw(2) = '0' then
motor_state <= STOP;
elsif sw(3) = '0' then
motor_state <= CWISE;
cw_45 <= '1';
elsif sw(4) = '0' then
motor_state <= CCWISE;
ccw_180 <= '1';
end if;
-- counter conditions
if cw_45 = '1' AND stepcount < 49 then
stepcount <= stepcount + 1;
elsif ccw_180 = '1' AND stepcount < 199 then
stepcount <= stepcount + 1;
else
ccw_180 <= '0';
cw_45 <= '0';
motor_state <= STOP;
end if;
case motor_state is
when STOP =>
drive <= '0';
stepcount <= 0;
when CWISE =>
drive <= '1';
CW <= '1';
when CCWISE =>
drive <= '1';
CW <= '0';
end case;
end if;
end process;
end stm;