Buses not showing in Xilinx ISE RTL schematic

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kmegamind

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in Xilinx ise, when i view the RTL schematic of a module, some buses are connected between the i/o ports and the module and other buses are not connected, what is the reason for this ?
This is an example for what i mean :
Select signal and output are not connected, while the rest is.
 

use the "view technology sschematic"
then you will see all the primitives being used, and the connections.
 

Thnx
But technology schematic show the look up tables
I want to see the design with all of its buses in the register level
How can i do that ?
And why are certain buses trimmed and other appear ?
 

kmegamind said:
Thnx
But technology schematic show the look up tables
I want to see the design with all of its buses in the register level
How can i do that ?
And why are certain buses trimmed and other appear ?
Click to expand...

from what i googled it look like the solution is to go back to an early version of xilinx and then it will show all connection (ise 8.2)
 

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