bulk to source connections in the cascod current mirror

Hello every one

is it right that in the cascode current mirror, if we dont connect the bulk to the source of the upper transistors it will lead to better circuit work ?? according to my friend that this will lead to create like a feedback voltage which correct the operation

for me I think it will lead to worse the circuit because the threshold voltage will vary more with the applied potential

Thank you very much

The latter. I support your opinion!

Thank you erikl for supporting me

erikl said:

The latter. I support your opinion!

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So erikl , if you are using the SOI technology, will you prefer to connect the bulk to source for every transistor ??

erikl said:

The latter. I support your opinion!

Click to expand...

Junus2012 said:

... erikl , if you are using the SOI technology, will you prefer to connect the bulk to source for every transistor ??

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In any case, if you can spend the additional area consumption for an extra SOI substrate cell. It's the same situation as for a pmos cascode in standard (p-substrate) CMOS process, where you can spend an extra nwell for the 2^nd transistor.

Junus2012 said:

Hello every one

is it right that in the cascode current mirror, if we dont connect the bulk to the source of the upper transistors it will lead to better circuit work ?? according to my friend that this will lead to create like a feedback voltage which correct the operation

for me I think it will lead to worse the circuit because the threshold voltage will vary more with the applied potential

Thank you very much

Click to expand...

I tried to answer this question myself because I did not know it by experience. Isolated NMOS devices with an isolated PWELL and PMOS could have connected source and bulk. In addition also SOI device could use that feature. The obvious drawback in a cascode is that the parasitic capacitance would be higher and therefore also the final compensated bandwidth would be lower. So there should be a good "DC reason" to make this connection. Because of the liftet potential of the source of the higher cascode device the biasing is little different. But that is no reason.

A simple reasoning could highlight what is the "DC-reason". If the drain voltage of the higher cascode device change by +1V for instance, the source potential of this device change by +50mV if the intrinsic voltage gain is 20. That lead to an increase of the drain voltage of the lower cascode device and an increase of current. Now because of the substrate or body effect of the higher cascode device the threshold voltage increase by +10mV because of the increase of source potential of +50mV. To supply the about the same cascode bias current the source potential must drop by about -10mV to supply the higher gate to source voltage at the same current. So the source potential lift of the higher cascode device is only +40mV because the body effect counteract the channel length modulation effect.

So your friend is right that for DC reasons it is better to have bulk not connected to source for the higher cascode device. It is a situation which should be memorized where AC and DC win.

Dear Friends

Now I am thinking in another way,

Since the voltage drop across the lower transistors are fixed to Von+Vth. where Von is the overdrive voltage. the change on the applied voltage is only handled by the upper transistors. therefore, the the VSB of the upper transistors are fixed coz the source voltage is the drain voltage of the lowe transistors which is fixed.

am I right ????

Thank you

B-S connection will make the guard FET have a lower,
natural VT while B-sub will raise it. This (B-sub) may
help or hurt leakage, depending on whether drain
leakage is or isn't gate-controlled @ OP. B-S on the
other hand imposes a shunt C in the middle of the
cascode which will change the dynamics of a current
mirror (at least on JI technologies where you're going
to be dragging a big well - substrate C around for at
least one type).

If you're using cascoding to stand off voltage beyond
D-G, D-S ratings, you have to also respect a D-B
limit which is not always clearly expressed (often a
B=S bias is assumed, for "digital" flows).