bulk tied to source layout

So I have a cascode NMOS in triple well. The top cascode NMOS its bulk is tied to its source. In the layout the NWELL is tied to VDD and bulk is connected to its source. But this NWELL is also connected to the bottom NMOS NWELL . Is that ok?

That sounds fine... from the processes I've used for layout in triple well (IBM .013u and STI 90nm), the bulks should be tied to the sources, the wells should both be tied to VDD and the bulk around the wells should be grounded...

so if this is what you did: Then you did it just fine!

is it necessary to add PSUB around NWELL? I know for better isolation it is recommended. Any other reason?

Well, technically the PSUB is a final connection outside of the NWELL it goes:
FET in PWELL (bulk for NFET)
PWELL in NWELL (NWELL ties to Vdd, like any NWELL)
BULK is grounded. This way, a cleaner diode forms between the NWELL and PSUB, PWELL and NWELL and such. This is all from the toolkit I used, again, and the schematic symbol was nicely labelled as such (there was a nfet, source connection, a forward diode representing the PWELL to NWELL which gets tied to Vdd, a reverse diode from the NWELL to PSUB that gets grounded (PSUB therefore must be grounded).

This is, of course, assuming you aren't bulk or well biasing the circuit. If you don't make that ground connect though, the performance of the FET will vary more than if you do, in my experience. I suppose it isn't completely necessary, but if you don't the FET will drift more - again in my experience.

Enjoy!