Building a Latch with for NANDS versus with a Multiplexer and two Inverters

[kvnsmnsn]

When I was first exposed to the idea of a D flipflop, and the latch that was its main building block, I was given the impression that the standard way to implement it was the four NAND gates in the following diagram that I got from "https://www.electronicshub.org/d-flip-flop":

                      ,---.
 data o---------------|    \         ,---.
                      |     )o-------|    \
              ,-------|    /         |     )o-------*-------o value
              |       `---'      ,---|    /         |
              |                  |   `---'          |
              |                  |                  |
              |                  `--------------.   |
nData o-------+---.                             |   |
              |   |              ,--------------+---'
              |   |              |              |
              |   |              |   ,---.      |
              |   |   ,---.      `---|    \     |
              |   `---|    \         |     )o---*-----------o nValue
              |       |     )o-------|    /
 gate o-------*-------|    /         `---'
                      `---'

Since each NAND gate has four transistors, this involves sixteen transistors, or eighteen, if you include the inverter that produces (nData) from (data). But since then I've seen an alternative way to build the same latch with just a multiplexer and two inverters:

                                           -------
                                              |
                            ,-----------------*-------------.
                            |                 |             |
                        ,---'                 |             |
                       ||                     |             |
                  ,---o||                     |             |
                  |    ||                     |             |
                  |     `---.                 |             |
gate              |         |                 |             |
  o-----*---------*         *---.             |             |
        |         |         |   |             |             |
        |         |     ,---'   |             |             |
        |         |    ||       |             |             |
        |         `----||       |             |             |
data    |              ||       |             |             |
  o-----+---------.     `---.   |             |             |
        |         |         |   |             |             |
        |     ,---*---.     |   |         ,---'         ,---'
        |    ||       ||    |   |        ||            ||
        *----||       ||o---+---*   ,---o||       ,---o||
        |    ||       ||    |   |   |    ||       |    ||
        |     `---*---'     |   |   |     `---.   |     `---.
        |         |         |   |   |         |   |         |
        |         *---------+---+---*         *---*         *---*-----o
        |         |         |   |   |         |   |         |   |    value
        |     ,---*---.     |   |   |     ,---'   |     ,---'   |
        |    ||       ||    |   |   |    ||       |    ||       |
        `---o||       ||----+---'   `----||       *----||       |
             ||       ||    |            ||       |    ||       |
              `---*---'     |             `---.   |     `---.   |
                  |         |                 |   |         |   |
                  |         |                 |   `---------+---+-----o
                  |         |                 |             |   |    nValue
                  `---------+-----------------+-------------+---'
                            |                 |             |
                            `-----------------*-------------'
                                              |
                                            .---,
                                             \ /
                                              v

Note that this circuit just has ten transistors, a considerable improvement over eighteen. Is there a downside to using this ten-transistor circuit to the eighteen-transistor circuit?

 

[BradtheRad]

Tutorials tell how all logic gates can be created with NAND gates. That and the fact you can build these in hardware simply from one or more 7400 IC's (quad NAND)... The idea is so entrancing that it sticks easily in a student's mind. I suspect it's been taught far and wide for decades until we rarely see other constructs mentioned. (Example, by using NOR gates we obtain inverted logic states.)

In fact when examining internals of certain logic gates (or FF's) we can identify sections made from two cross-biased NAND gates. That's related to a memory cell. In simple form this is SR flip-flop made from two cross-biased transistors. Perhaps (I didn't check your design) you found a way to assemble a DFF from these simpler building blocks.

 

[FvM]

Transfer gate is the standard latch implementation in CMOS, look e.g. at 74hc74 master-slave flip-flop

 

[dick_freebird]

For some reasons like single event upset resistance I still prefer the NAND latch. But the TINV latch offers more tweakability in setup / hold and is likely faster, more compact.

 

[kvnsmnsn]

Perhaps (I didn't check your design) you found a way to assemble a DFF from these simpler building blocks.

That was the question I asked. Is my design an improvement over cross-biased NAND gates? Or is there a downside to using pass transistor logic the way I used it? I realize that pass transistors are non-restoring, so noise could work its way into my circuit, but the first thing I do with the output is feed it into a restoring inverter, so it didn't look to me like noise had much of a chance to build up over time.

 

[kvnsmnsn]

Transfer gate is the standard latch implementation in CMOS, look e.g. at 74hc74 master-slave flip-flop

View attachment 197145

FvM, I still counted 32 transistors in this design. If this is a full flip flop, then my design would create a flip flop from two latches, each with eight transistors, and I'd need two more transistors to give me the inverse of my clock, hence 18 transistors in total. Doesn't that make my design more efficient? I ask again, is there a downside to my circuit that uses a multiplexer?

 

[kvnsmnsn]

For some reasons like single event upset resistance I still prefer the NAND latch.

Dick, I haven't quite finished a set of courses in electrical and computer engineering at UVU. Could you explain to me what single event upset resistance means, and why it would lead you to prefer the NAND latch? I kind of like the ten-transistor latch I happened across, but I would like to know what its weaknesses are in addition to just its strengths.

 

[dick_freebird]

The TINV latch can be, but often is not very "strong" in the latched state because library designers favor short setup time and shrink the feedback branch (which presents a counter-drive that the forward path has to overcome before the clock edge gets there).

Single event phenomena come from energetic particles transiting a device. If the ion drops more energy in the device volume than represents a bit (charge) there is then a chance that you'll flip the bit. You can also see such transients amplified, stretched, captured elsewhere. The collection current can also provoke worse things but that's not on-topic for a latch topology question.

It's a big deal in space, somewhat for high altitude aviation and even data centers at high elevation. The latter consisting of a sh!t-ton of memory bits as targets.

 

[FvM]

FvM, I still counted 32 transistors in this design. If this is a full flip flop, then my design would create a flip flop from two latches

You apparently didn't understand my comment. I just wanted to show that your suggested "multiplexer" respectively TG latch is industry standard implementation. The posted MS FF schematic uses two of it plus additional preset and clear logic. If you omit preset and clear, it reduces to two copies of the circuit you suggested in post #1.

 

[BradtheRad]

To build with mosfets requires you to pay attention to compatible volt levels. There's the matter of how to drive two mosefets totem-style or half-bridge arrangement. Do they change state at supplyV/2 or at an individual threshold? Does changing your supply voltage still maintain your FF operating as expected?

Does it successfully divide-freq-by-2 when you attach bar-Q output to D input?

Can your design easily be cascaded into several stages if we wish to build a counter or shift register?

 

[dick_freebird]

You apparently didn't understand my comment. I just wanted to show that your suggested "multiplexer" respectively TG latch is industry standard implementation. The posted MS FF schematic uses two of it plus additional preset and clear logic. If you omit preset and clear, it reduces to two copies of the circuit you suggested in post #1.

The latches shown are often called "half-latches", I guess because they each do half of the FF job.

 

[dick_freebird]

That was the question I asked. Is my design an improvement over cross-biased NAND gates? Or is there a downside to using pass transistor logic the way I used it? I realize that pass transistors are non-restoring, so noise could work its way into my circuit, but the first thing I do with the output is feed it into a restoring inverter, so it didn't look to me like noise had much of a chance to build up over time.

NAND version is likely slower when made with
real and reasonable FET sizes. That's my experience.

The "baggage" of inputs and gates that "only get
used once" (the case with modern blessed fully
synchronous design styles) can be put "off to the
side" in TINV logic, inverter plus TINV will be
"lighter weight" than the NAND3 (or stacked
NAND2s) you will need to add to speed-critical
paths to bring in set and reset terms.

That "baggage" C and less-wimpy drive in the
feedback paths toughens up the NAND 'flop
against narrow noise impulses. At the cost of various
timing attributes (delay, setup).

TINV style was not viable in predecessor bipolar
logic families (even inverters have 5 NPN transistors
in 74xx TTL and lineal descendants) and tri-state
even more; NAND gates only add 1-N more emitters
to the existing front end transistor base. So NAND
'flops (or cross coupled resistor loaded core, for RAM)
was the way.