Building a 80486 S-100 Bus CPU board.

[monahanz]

I tried posting this message in the Professional Hardware and Electronics Design section. Got no comments.Though I would try here.

I am one of a small group of people that like to build new boards for the 1980’s era S-100 bus.
I have a web site (www.S100Computers.com) which gives the details.
We just finished doing a new 80386 Master/Slave S-100 prototype board (along with 8 and 32MG Static RAM boards). It is described here in case anybody is interested:-

**broken link removed**

The board is real fun and works reliably with a 32MH clock. We hope to do a “production run” for people interested early next year. (bare boards are at cost, ~$20 each).

Anyway the point of this message is I would now like to do an 80486 board. Reading the Intel manuals it appears as if the two CPU’s have a lot in common and it should not be too difficult.

There is one major difference however. Intel says (unlike the 80386) the 80486 does not shift down 16 bit data to the lower 16 bits of its 32 bit data bus. Apparently you need extra buffers (74LS373’s etc.) to externally shift all four 8 bytes as needed.
One extra feature of the 80486 is it has a “bs8#” Pin that Bus Sizes its data I/O to 1, 2, 3 or 4 eight bit bytes. They are sent back to back (like the old 8088’s). This is a very useful feature for the S100 bus and considerably simplifies the interface.

My question is this (finally), does the 80486 still present the 8 bit bytes (address +1,+2 and +3) on the Data 8-15, 16-23 and 24-32 lines or when bs8# is low send all the data out on data lines 0-7 irrespective of BE0#-BE3#.

Hope I have framed the question clearly. If not please let me know.
John

 

[betwixt]

I'm going back a long way to the days when I worked on 386/486 systems but I think you are right about the byte alignment. The original IBM PC motherboards used four latches in what they called "cycle conversion logic" which if I remember correctly was a latched steeering system to align the data from the 486 to the lower bits on the data bus. Unfortunately, I no longer have schematics to verify this. I have got some 386 PC motherboards and 486 PC motherboards here but it would take too long to wire them up and write a test program to verify their operation, besides, I think they are just about recent enough to use LSI bus controllers so gaining access to the signals might be impossible.

Brian.

 

[monahanz]

Thanks for help betwix. It's a bit complicated because most motherboards of that era were 16 bits and would have to incorporate the full set of 8 bit shifts for the 4 sets of 8/32 bits of data not 8 bits only as I want to do.

What I am considering is strictly an 8 bit data bus output with the CPU forced to do back to back byte transfers (activating the CPU bs8# pin). This is quite different than a “normal’ 32 bit shift down transfer since it is done outside the CPU. I’m not sure a typical motherboard would incorporate this. Probably bs8# would only be used by dedicated controller boards etc.
Unfortunately it’s very important I know the answer before I lay out the board because the CPU support circuitry is very different. It if I can get away with just using the lowest 8 bits things get very simple.

I know people will argue this downgrades the CPU speed. But remember it’s just the lowest 16M of RAM that will be configured as such, all the rest (4GB) will be 32 bits wide. Also I’m counting on the CPU onboard cash to speed things up a bit.
Anybody else have any info.

John

 

[FvM]

May be I misunderstood the question, but the discussed x486 problem is only about acessing 8 or 16 bit entities on 32-bit respecticvely 16 bit data bus. E.g. write 8 or 16-Bit data to arbitrary positions of a RAM on a 32-bit bus.

But as you plan to connect a 8-bit S-100 bus, it can be wired to the lower 8-bits of the x486 bus.

 

[monahanz]

Are you absolutely sure of that, because if that's the case things are very simple, if not I have a non-repairable prototype board.
In other words if bs8# is pulled low the data (no matter what the address/BS0-BE3) will ALWAYS appear on data lines 0-7.

One way to be sure would be to find an 80486 motherboard circuit that has a single BIOS ROM. I just cannot locate a schematic for that. Would be very comforting!

 

[FvM]

It depends on the intended mapping of the S-100 bus. If you want a continuous address space to perform hardware DMA or block transfers, you need 4-to-1 byte multiplexing (as also described in 386 hardware manual). When talking to S-100, a 486 would be unemployed enough to do these things virtually instead in hardware, but the idea possibly won't fit your software concept.

The link in your first post is invalid, by the way. It's the copy of a "..." placeholder.

 

[monahanz]

Thanks, looks like I will have to do the 4 to 1 multiplexing.
That said, I missing then what the bs8# input signal is used for.
When would you use it?

Here is the missing URL you mentioned
http://www.s100computers.com/My System Pages/80386 Board/80386 CPU Board.htm

Thanks
John

 

[FvM]

The 8-Bit and 16-bit bus access methods are explained in detail in the Embedded Intel486(TM) Processor Hardware Reference Manual http://www.pld.ttu.ee/~prj/486dev.pdf

bs8# has to be asserted to inform the processor that the selected memory region has 8-bit organization. 16 and 32 bit accesses are then split into byte accesses.

 

[monahanz]

Sorry to drag this out, but I need to be clear. With bs8# asserted then and say a 32 bit memory write starting on an even address:-

ADS pulses low, address latched, first byte on data lines 0-7, R/W strobe sent
next byte, ADS pulses low, address +1 latched, second byte on data lines 8-15, R/W strobe sent
next byte, ADS pulses low, address +2 latched, third byte on data lines 16-23,R/W strobe sent
next byte, ADS pulses low, address +3 latched, fourth byte on data lines 24-31,R/W strobe sent

Is this the correct order or is it all reversed. I cannot see this described in the manual.

Really appreciate the help
John

 

[FvM]

Why reversed? General x86 architecture characteristics are taken as granted.

For a complete answer, e.g. bus timing, you should review all relevant 486 and embedded 486 documents.

 

[monahanz]

Was thinking of high byte/low byte Intel RAM storage format, but I guess if I use BHE0-3 I don't have to worry about the above anyway.
So if I have it correct the four BHE's will always tell me which 8 bits to place on the S-100 bus, internally the 80486 will match data with addresses every time.
Correct yes/no?

John

 

[FvM]

Yes, should work this way.

 

[monahanz]

A schematic for a dedicated controller using an 80486

I am in the process of building an 80486 CPU board for the S100 bus.
See for example:-
http://s100computers.com/My System Pages/80386 Board/80386 CPU Board.htm

It would help me greatly if I could find an example schematic of a 80486 dedicated controller schematic.
Has anybody got a schematic of a circuit driven by the 80486 family of CPU's. All I have to go on right now is the Intel "hardware reference manual". Would be nice to see an other/detailed examples.
The Barry Brey book is really skimpy when it gets to these "later" CPU's.

 

[monahanz]

Re: A schematic for a dedicated controller using an 80486

Perhaps this is not in the right location on this forum?
Anybody got any suggestions?