raduga_in said:Pushpull Class AB buffers can be an option ..
Raduga
Octago said:In my circuits, I want to design a buffer in order to drive a large capacitive load
For example, a source follower is often used in this case as a buffer
But the source follower always introduces a voltage drop between the two stages, which is not desired in my case.
So are there any buffers which can on one hand drive a large capacitive load, but on the other hand not introduce any DC voltage drop?
Old Nick said:Octago said:In my circuits, I want to design a buffer in order to drive a large capacitive load
For example, a source follower is often used in this case as a buffer
But the source follower always introduces a voltage drop between the two stages, which is not desired in my case.
So are there any buffers which can on one hand drive a large capacitive load, but on the other hand not introduce any DC voltage drop?
A simple OTA (long tailed pair), with -ve feedback is what I normally use, far superior linearity to a SF aswell.
spminn said:I think a CMOS inverter with a feedback resistor between input and output should do the job. It would have enough current drive due to the addition of gm of the pMOS and nMOS and the resistor should set the output bias to be the same as the input bias.
leohart said:Old Nick said:Octago said:In my circuits, I want to design a buffer in order to drive a large capacitive load
For example, a source follower is often used in this case as a buffer
But the source follower always introduces a voltage drop between the two stages, which is not desired in my case.
So are there any buffers which can on one hand drive a large capacitive load, but on the other hand not introduce any DC voltage drop?
A simple OTA (long tailed pair), with -ve feedback is what I normally use, far superior linearity to a SF aswell.
what is -ve feedback pls?
Added after 2 minutes:
spminn said:I think a CMOS inverter with a feedback resistor between input and output should do the job. It would have enough current drive due to the addition of gm of the pMOS and nMOS and the resistor should set the output bias to be the same as the input bias.
can this one work? it has gain only in a small portion near the middle of input voltage, and what is the purpose of the feedback resistor?
Octago said:thanks
But if I use a OTA with unity feedback as the buffer, will the problem of oscillation be critical?
Old Nick said:Octago said:thanks
But if I use a OTA with unity feedback as the buffer, will the problem of oscillation be critical?
I use them all the time, and not one of them has oscillated, ever. If you're feeding it with square waves then I wouldn't put my mortage on it not oscillating a bit, but if you're worried about it do a few sims.
jecyhale said:You can rebias the DC level by a couple capacitor and a resistor if the frequecny is very high.
And if the frequency is not very high, it will not care the large capacitor.
So can you tell us the frequency and the capacitor value?
Octago said:The frequency is no more than several KHz
the capacitive load needed to drive will not be more than 50pF
jecyhale said:You can rebias the DC level by a couple capacitor and a resistor if the frequecny is very high.
And if the frequency is not very high, it will not care the large capacitor.
So can you tell us the frequency and the capacitor value?
tia_design said:How big the capacitor load is. I think Class AB is a potentialchoice
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