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buffer spec in pipeline ADC

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M

mists

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When I design the 10b 40M pipeline ADC, to save output pin, I can't use large capacitor to stabilize the reference (VREFP and VREFN) voltage on board, I must stabilize them internal chip. Then how to define the buffer spec (include bandwidth, slew rate and gain) which is used to generate reference voltage? thanks!
 

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