both buffer insertion and gate sizing can be used for delay optimization, i think most eda tools can try to resolve delay ploblem when under proper constrains using these two methods. you can google the two key works "buffer insertion" and "gate sizing" for more information. good luck!
If you have STA results this would give you good indication whether to up size or down size cell. It all depends on delays on that path but you must take care that you do not cause skew conditions to other paths!