buffer architecture aside from taper buffer that can drive clock for 1uF load

[allennlowaton]

Hello EDA fellows,
I would like to ask your advises about any buffer architecture that can drive/provide clock for a very large capacitor (1uF).I tried to use taper buffer but it's extremely big (the MOS width reaches 20,000 already)...
Thank you.

 

[dick_freebird]

Well, you're not going to get away from a big device if you want to drive
a big cap.

However you do want to play with anti-shoot-through when you get to
monstrous drivers.

Why there is a 1uF load on anything called a "clock", I couldn't imagine.
If it is many parallel loads then distributing predrivers could make
sense for several reasons.

 

[allennlowaton]

I'm going to use that buffered clock for this pump circuit shown below:


C3 and C4 are 1uF capacitors.

 

[leo_o2]

Just use taper buffer. Please add dead-time control. Also pls be careful for ground bounce.

 

[allennlowaton]

Just use taper buffer. Please add dead-time control. Also pls be careful for ground bounce.

Is it recommended for me to use non-overlapping clock generator for this case?

 

[leo_o2]

It is correct.
Ground bounce can be controlled by slew rate.