Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Can anyone tell me which is the best
Connecting two inverters in series or a single buffer???
if yes why??
I need good explaination on this..............
it depends on the propagation delay... if you want more propagation delay then two inverters is a good way but at the cost of excess power dissipation...
I didn't get u
can u explain me more clearly
buffer adds delay it will not reduce delay it will increase the delay i think bcoz whn we add buffer in the case of clock to flop it will add the delay right??
If it reduces power consumption then we can use buffers then why the two inverters is the best???
can u explain me in detail??
Added after 2 minutes:
hello srinivas
If we want more propagation delay then we can use buffer right instead of two inverters in series...
thn why we are not using those in the case of timing??
propagation delay of a gate is fixed for a particular logic family and if the buffer cannot provide the required propagation delay then we go for the two inverter....
in most logic families usually buffers are implemented using two inverters and hence there is no difference between the two....
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.