Bubble sort algorithm in verilog

Hi, I'm trying to implement a bubble sort algorithm in Verilog. Essentially, i have 20 numbers in my RAM, and i need to sort them from lowest to highest. The method is by comparing the 1st and 2nd number, and switching them if the 1st is bigger than second. The same is done for 2nd and 3rd, 3rd and 4th until the highest number is at the end. This is repeated till the 2nd largest number is at the 2nd last position etc etc until it's fully sorted. I'm using a state machine, and i keep getting an error: "can't resolve multiple constant drivers for net", and this shows up for almost all my variables. I have no idea what to do, so any help would be much appreciated! thanks! The code is below:


module question3(clock,start,q_a,q_b,wren,state);

input clock; //declare clock
input start; //start button
output [7:0] q_a,q_b;

parameter [2:0] IDLE=3'b000, ADDRESSES=3'b001, READ=3'b010, COMPARE=3'b011, WRITE=3'b100;

reg [7:0] next_j=8'd0, j=8'd0, data_a=8'd0, data_b=8'd0, next_max=8'd18, max=8'd18, next_counter=8'd0,counter=8'd0;
output reg [2:0] state=IDLE;
output reg wren=1'b0;
reg [2:0] next_state;



always @(posedge clock or start)
begin
if (!start)
begin
next_state<=IDLE;
end
else
begin
j<=next_j;
counter<=next_counter;
max<=next_max;
state<=next_state;
end

end

ram_2port ram1(j,j+8'd1,clock,data_a,data_b,wren,wren,q_a,q_b); //instantiate RAM

always @(state or j or max or counter or q_a or q_b or data_a or data_b)
begin
case (state)


IDLE: begin
j=8'd0;
max=8'd18;
counter=8'd0;
next_state=READ;
end



ADDRESSES: if (j==max)
begin
next_max=max-8'd1;
j=8'd0;
counter=8'd0;
next_state=READ;
end
else
begin
next_j=j+8'd1;
next_state=READ;
end

READ: begin
wren=1'b0;
next_state=COMPARE;
end


COMPARE: if (q_a > q_b)
begin
next_state=WRITE;
end
else
begin
if (counter==max)
begin
next_state=IDLE;
end
next_counter=counter+8'd1;
next_state=ADDRESSES;
end

WRITE: begin
data_a=q_b;
data_b=q_a;
counter=8'd0;
wren=1'b1;
next_state=ADDRESSES;
end

endcase

end

endmodule

next_state is defined in two processes. j is defined in two processes. counter is defined in two processes. max is defined in two processes. next_max is never defined. next_j is not defined. data_a and data_b are latches.

permute said:

next_state is defined in two processes. j is defined in two processes. counter is defined in two processes. max is defined in two processes. next_max is never defined. next_j is not defined. data_a and data_b are latches.

Click to expand...

Not sure what you mean? Is it because I define them in 2 seperate "always" blocks? That shouldn't be a problem, should it? I've seen state machines that do that...i think. Would u be able to show me how to correct the code?

That shouldn't be a problem, should it?

Click to expand...

If you're not that familiar with Verilog rules, the Verilog compiler already answered the question. "Multiple constants drivers" is the exact result.

I've seen state machines that do that...i think.

Click to expand...

You may want to review the said examples. Usually state is set in the clock synchronous (posedge clock) always block and next state in the combinational block. Following the same scheme, all true registers are set under posedge clock.

As you are apparently using Altera Quartus (according to the RAM port names), you can also review the state machine Verilog templates from the editor context menu.

jpglotzer said:

Not sure what you mean? Is it because I define them in 2 seperate "always" blocks? That shouldn't be a problem, should it? I've seen state machines that do that...i think. Would u be able to show me how to correct the code?

Click to expand...

The state machines with multiple "always" blocks sure as hell will not try to drive the same signal twice.

I was working on a FSM just now, and it is one of the three-always statements variety. One for the "state" update on posedge clock, one for the combinatorials for next state, and one to register all the outputs on posedge clock.

But all of these signals are driven by only one of the always blocks each.