yes,but what I meet is that some pin I don't know how to define,such as some signal port output pull down resistor enable .There is nothing can map it .
for example :
generic io
module bidi_enable_high (pin, dout, oe, din);
inout pin;
input dout, oe;
output din;
endmodule
module my_bidi (signal_do,signal_oe,signal_pd,signal_pu,signal_pin0,signal_pin1,signal_c,signal_en,pad_out,vref_pioa,signal_rcomp,test_en);
inout ..;
input ..;
output ..;
endmodule
specparam mgc_dft_cell_type = "bidirectional_pad";
specparam mgc_dft_pin_type$c=signal_c = "pin";
specparam mgc_dft_pin_type$pad_out = "dout";
specparam mgc_dft_pin_type$signal_do = "din";
specparam mgc_dft_pin_type$signal_en = "oe";
//but there is a question about how to map the rest signals.whether should i map those signals to nonexistent?
endspecify