brain twister for gurus, can you make it slower

I encountered some design challenges and want to share it with my fellow experts. Actually it's an interesting topic for contest.

Given a high speed HBT process, all you can have are:
NPN bipolar transistor(number unlimited, ft=100G, beta=50), caps (MIM cap, tot<20pF), resistors( tot < 100k), inductors (tot < 5nH), supply (3.3v).

Goal: design a low speed amplifer with gain of 40dB, GBW of 10kHz.

Restriction: you can not use any external caps.

Background: I always think about making a low speed amplifier using high speed devices without external components (caps). Some people tried in LDO design, but not as the condition is not as dramatic as the one mentioned above.

firstly I must say it is a wonderful goal !!!

but I think it is possible to compensate an amplifier with the a dominant pole at low frequency with a large capacitor; I know the problem is the large capacitance value but it can be solved by simulating it with a "miller-ed" small capacitor, i.e. using a small capacitor and a high gain amplifier for "amplifying" its value!

BEST!

Good point. Dominant pole using voltage type cap multiplier.
Let's do some estimation:

Since GBW=10k, DC gain =40dB, the single pole is located at 100Hz.
To creat such a low freq. pole, your dominant RC constant is 1.6ms.
Note this process is NPN only, without resorting to negative resistance scheme, the highest single ended impedance you can make is a pull up resistor. Say you use 10kOhm, therefore a 0.16uF cap is needed.

A cap multiplier, i.e. miller effect cap, functions as a cap with value equal to feedback cap times voltage gain. Because tot 20pF is permitted, you need gain 0.16u/20p=8k. Hence you need a 78dB amplifier. It's not quite easy to do in NPN only process. Given the chance you can design as it is, note since it's a very high speed process, what about a slight possible coupling between input and output. Your main amplifier gain 40dB, your miller amplifier gain 78dB, total 118dB, is it possible to oscillate?

How about go to negative resistance compensation? Let's say We want to realize a high resistance by feedback. Say to make 100k equivalent resistor, it shall be a real resistor parallel with a feedback negative resistance. Let's assume the real resistor to be 10kOhm like before, the negative resistor shall be -11.1k. If the process variation is +/-10%, you can feel the threat of a possible latch up, right?

That is like sport. Or chess. I like it!

The allowed components are only NPN, 100kOhm total and 20pF total, right?

Q:

1. Gain is voltage gain?
2. Input impedance is not specified?
3. Output impedance?
4. How accurate should the 100Hz or the 40dB?

What is the price?

BTW: No Job offer.

rfsystem said:

That is like sport. Or chess. I like it!

The allowed components are only NPN, 100kOhm total and 20pF total, right?

Q:

1. Gain is voltage gain?
2. Input impedance is not specified?
3. Output impedance?
4. How accurate should the 100Hz or the 40dB?

What is the price?

BTW: No Job offer.

Click to expand...

Absolutely correct:
NPN, 100kOhm total and 20pF total

A:
1. It's a voltage gain 40dB.
2./3. don't worry about input/output impedance. We can fix them later.
3. Tol for pole and gain is assumed 10%
Actually our target is to make it slow. Other specs are very trivial.
So far don't worry about nonlinearity, offset, noise, SR, etc.

Price: A smart and creative solution guarantees a good journal publication. You are the first author. I would try to make it happen.

BTW: Author of the great solution can send me a resume. We are looking for somebody like this. Does it sound like an interview question? The only problem is I don't have a definite answer yet. Possible approach:
1. log domain filtering (translinear)
2. switching type (not only SC type, but more general, what about PWM scheme?)
3. possibly a brutal force mixed signal design, a ADC + Digital filter + DAC, or a little bit smarter way using PLL?
They are all open to us! The only important thing is creative thinking.