Boundary scan insertion

Can anyone please reply to this post?

The DFT structures are inserted usually by the synthesis tool, so Genus for Cadence and Design Compiler for Synopsys. The typical flow is to get a first synthesis to pass. Then you go adding the DFT commands until you get it like you want. This includes boundary scan, regular scan chain, MBIST, perhaps LBIST, and perhaps a JTAG IP. The tool does create some files that will be used by the P&R too.

[QUOTE="glennramalho, post: 1773888, member] . The tool does create some files that will be used by the P&R too.
[/QUOTE]

What are these files and what are the purpose of these files which are created by the tool?

What do the P&R tool do with these files?

Depends on the tool and the exact DFT features you are using. I never inserted the boundary scan, but from other DFT commands I have done I know you need to define the jtag instructions, define the JTAG registers, and create them using Genus commands. You might need to crea an iospec file. You can use add_jtag_boundary_scan -preview and write_dft_jtag_boundary_file can be used to get a template, modify and then use it.

Files generated, asside from the netlist, reports, and so on, Genus will also generate a BSDL file, for generating the sequences for testing the board and a final IO spec file which will have the exact order of the pins and some features used. Additionaly it is a good idea to let genus generate SDC files for innovus, with timing constraints for the functionality Genus added. The P&R will need some of these files, the BSDL is more for the testers.

You will have to go through the manual though for a complete list of files, but I think this is a starting point

I hope this helps

you can use Siemens Tessent Shell/Cadence Genus/Synopsys Testmax DFT for inserting boundary scan as per your need.

jishnuv33 said:

you can use Siemens Tessent Shell/Cadence Genus/Synopsys Testmax DFT for inserting boundary scan as per your need.

Click to expand...

Well, almost. The actual DFT logic is inserted during synthesis, so Cadence Genus or Synopsys Design Compiler. I have no idea what you do in Mentor, I guess it is tessent, but I am not that familiar with their tools. This is only to implement the design changes to put in the DFT. These programs also generate the files you need to feed to your tester pattern generation software.

For pattern generation for the ATPG testers (scan chain, MBIST, etc) you use Cadence Modus or Synopsys TetraMAX/TestMAX.

For boundary scan, being it is done at board level, you then the board design software has that capability, but I am not that familiar with the software tools here.