papanatas
Newbie level 6
Hi there, i'm new to this world and currently playing around with magic and irsim to understand how vsli cells work.
I'm wondering if anyone can give me a hand to understand how to represent what this 3-input gate below, i'm failing to understand how to representing in boolean or what combination of gates can reproduce such result.
In summary, when A is low and C is high, then the output (Q) is C, when A is high and B is high, then the output (Q) is B....
Thanks for the help!
Truth table
A B C Q
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
- - - Updated - - -
Hi again, just found what it is.... it's a 2x1 mux with A being the Select bit, thanks for reading.
I'm wondering if anyone can give me a hand to understand how to represent what this 3-input gate below, i'm failing to understand how to representing in boolean or what combination of gates can reproduce such result.
In summary, when A is low and C is high, then the output (Q) is C, when A is high and B is high, then the output (Q) is B....
Thanks for the help!
Truth table
A B C Q
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
- - - Updated - - -
Hi again, just found what it is.... it's a 2x1 mux with A being the Select bit, thanks for reading.