Bonding Wire in Cadence Virtuoso

I seldom find bond wire or package feature layers in the
primitive / ancient technology PDKs I use. I tend to use
text/dwg layer as this is one of the "universal" ones
Cadence knows regardless of assigned process technology.

I use "Create>path" with "anyAngle" selected (F3 or right click
once you're in it) and the width set to 25 (1 mil Au) or
30 (1.25 mil Al wire).

Since my communication with assembly houses is all just
Powerpoint or PDF files nobody cares what layers you use
in Cadence. Maybe if you wanted some EM solution from
a tool that demands specific construction.

Dear freebird,

Thank you very much for your nice explanation,

That is really helped me, my mistake is that I have used create wire instead of path, which dosent support the route with any angle. With your suggestion is working, and by the way I find it from Create > Shape> Path.

I think this solution can only work with simple DIL package types, moving to more complex packages requires APD (Allegro Package Designer)or Virtuoso RF Solution.

Please see the attached image, the DIL package is imported by steam, and it is required from me to add text on the description field, but I am did not find a tool for adding text in Layout editor, how can I add text and on which layer?

Thank you once again for your help

What I would do, is save this figure as your own layout master
and edit (or edit in place) the various texts within it. Then it
becomes the design-specific package and not generic.

I've followed the described approach for every DIP, SO,
quad package I've had occasion to use, up to about 192
pins. Beyond that you get into area array packaging that
I've never had to make a detailed drawing for - we used
an Excel sheet w/ a cell per pillar on a 384 (-1) package
last time I touched anything that big. The last mile was
Somebody Else's Problem. I'd bet that in the intervening
decades somebody has declared a "methodology" and
figured out how to price a point tool license.

Thank you freebird, you have solved my issues to this step.
As you said the housing foundry will not care for which layer you used for the plotting the bonding wire or for adding the text, so I used create Label and selected the layer TEXT and filled the forms.

One question remaining please for the bonding process, I have read that bonding wire length are calculated from the center of the chip bonding pad to the center of package pin, However, when I look to micrograph of some fabricated chip, I see that the bonding wire is not coming to the center of the package pin, mostly to the first 30 % distance from the chip side.

I would like to know from your experience regarding this point
Thank you
Best Regards

Yes, I usually see (and so, draw) the post foot at about 1/4 to
1/3 of the way in from the bond shelf edge. Too much more
and the bonder capillary may interfere with the seal (lid)
shelf (if we're talking ceramic solder seal hermetic packages,
which I mostly use).

A stamped leadframe, plastic mold package ought to not
have the same concern. But having done almost no work
using plastic packaging, I couldn't say what issues there
might be in the "design space".

One potential (if second-order) interest might be the
difference in resistance between a length of bond post
finger, and a length of bond wire. More of one means
less of the other, a length trade. I do know that the
cofired ceramic packages use fairly resistive metal inks
(tungsten, or molybdenum are your choices and not much
difference, neither are great) while the bond wire Al, Au
(or Cu?) are all much better conductors. In the rollup of
the entire post-to-pin trace however, you're talking about
scraping for a percent or three of total pin-to-pad R if it's
a large body like DIP40 or CQFJ84, or a complex custom
CLGA with fine pitch internal routes. You might elect to
pick a worse case of known geometries and work out
the numbers, and whether to try harder on the post
location (with the input from the assembly engineers).

thanks freebird, that was a nice explanation,
and this lead me to the next question, I have read the bonding rules of the my housing foundry, they specifiy that max wire angel between the norm of the chip pad to the middle line should be less than 45°, and you know that angel will be different if the bonding wire done to the middle of the package pin from the other place if you for example attached it to the 1/4 area,

what you follow for this rule

thank you

I will cheat on this if need be (I have never noticed this rule)
but a normally arranged pad ring will naturally be between
zero and 45 degrees bond wire angle to the corresponding
post-rank normal line.

I've had sea-of-pads test chips where I've run wires out
sideways on the ends, and so on. IMO "rules" like this are
"negotiable" (if you try). Production, however, wants you
to follow rules if you can do it by layout and pin assignment.

Thank you freebird,
it is a wonderful to have help based on your experience,
for your interest as well, I am sharing you with you the bonding rules that I am trying to fulfill, it is not confident information and you would be able to reach it online, plese see the section 2.3


by the way you are absolutely right, if you have many pads then you not even wary about the angle cause it will always come with less than 45°

I don't know why they mentioned about the center of the package pin while in the example they give they are not trying to do as you can see below (this example is from the assembly hausing),



So as you mentioned even when you run wires out sideways on the ends it should not be a problem.

One important question please, is the bonding wire machine follow exactly the line you plot to connect the pad to the pin, or these wires are only like labels and have no physical meaning, just to indicate there is connection between this pad and that pin and the machine will decide where it will make the solder joint?

Thank you

Best Regards