Bode plot of opamp integrator

[zenerbjt]

Hi

Why does the LTspice AC simulation give the phase near the f=0 axis as 180degrees for this opamp integrator?
This cannot possibly be right. Surely?

The transfer function is – (1/jwC)/ R,

...Which equals 0 + j (1/wCR)

...The phase of this is atan {[1/wCR]/0}

..this is atan (infinite) which is n.pi/2, where n = +/- 1,3,5,7,9 etc

This cannot possibly be 180 degrees. Do you agree?

 

[Dominik Przyborowski]

Signal is going into inverting input and loop is open, so 180deg phase shift in low frequencies is expected.

 

[FvM]

It's the stupid simulation setup. An integrator in open loop will never achieve a useful bias point.

 

[FvM]

Same simulation with useful DC bias

 

[LvW]

Hi

Why does the LTspice AC simulation give the phase near the f=0 axis as 180degrees for this opamp integrator?
This cannot possibly be right. Surely?

In your simulation setup I see a REAL opamp model (finite open-loop gain Aol).
Provided that the offset voltage of the opamp model allows a DC bias point within the quasi-linear operating range the closed-loop gain at w=0 is

Acl=Aol/[1+Aol*sRC/(1+sRC)] >>>>> Acl=Aol for s=jw=0.

Because of the opamps inverting operation the phase of the open-loop gain Aol at w=0 is -180deg.

 

[FvM]

Because of the opamps inverting operation the phase of the open-loop gain Aol at w=0 is -180deg.

That's surely correct, but the OP is actually talking about the phase at 0.1 Hz, described very unclear as "phase near the f=0 axis".

 

[sutapanaki]

For sure the closed loop integrator characteristic can not be higher than the open loop gain of the amplifier itself. At some low frequency the integrator ac response will hit the DC gain of the opamp and stop there.

 

[FvM]

For sure the closed loop integrator characteristic can not be higher than the open loop gain of the amplifier itself. At some low frequency the integrator ac response will hit the DC gain of the opamp and stop there.

Yes, but not in the frequency and gain range of the simulation circuit. Integrator gain at 0.1 Hz is about 65 dB, LT1006 DC gain is > 120 dB.

 

[LvW]

Yes, but not in the frequency and gain range of the simulation circuit. Integrator gain at 0.1 Hz is about 65 dB, LT1006 DC gain is > 120 dB.

Yes - but below 100mHz the simulation results (down to 1µHz, near DC) with the shown setup (post#4) are not realistic because the ac source is not referenced to ground but to the opamp output.
Therefore, I propose to make an offset compensation with app. 130µV DC at the non-inv. input.

 

[FvM]

The purpose of the simulation circuit is to get correct bias without affecting the integrator transfer function down to 0.1 Hz, but not 1 uHz. There are of course other ways to solve the simulation problem.

I'm not sure how you derived 130 uV offset. With typically 140 dB DC gain, the unknown offset voltage and it's drift have to be compensated with < 1 uV accuracy if you want to avoid DC feedback.

 

[LvW]

I'm not sure how you derived 130 uV offset. With typically 140 dB DC gain, the unknown offset voltage and it's drift have to be compensated with < 1 uV accuracy if you want to avoid DC feedback.

The answer is no surprise - I followed the classical way for finding the input offset:
DC analysis of the opamp model (LT1006_LT) without any feedback. The DC output crosses the zero-volts line at +131.5µV (increment during simulation 0.1µV)

 

[FvM]

Some OP models have built-in arbitrary offset voltages and -currents. I found that in case of the LT1006 model, uos and ios are zeroed, input bias current is the only relevant source of circuit offsets. Respectively the simulation setup can be considerably simpified: