Board design DDR3 and DDR2

[iliya24]

Hello
I facing a problem to give an instractions set of recommendation for board design of DDR and DDR3 i have read some application note from altera and Micron .
But the all a little bit complex for me have u any suggests for me?
Thx.

 

[sivamani]

refer
https://www.edaboard.com/threads/288915/
https://www.edaboard.com/threads/283545/

 

[amitjagtap]

Check this material ...

The most common type of DDR trace routing is a series/parallel termination scheme using a 50-ohm
transmission line model. This scheme is used on the M54455EVB, and is easy to see in Figure 3. Looking
left to right, the series resistors are located very close to the ColdFire processor, and the parallel
termination resistors are located just to the right of the DDR2 memories. The following are key concepts
for the series/parallel termination scheme and how it is applied to DDR/DDR2 board designs:
• Series terminators must be placed close to the source driver. This example uses single series
termination. This means that only one set of series terminators are used, and they are placed next
to the ColdFire processor. A dual series termination scheme can be used, but is rarely necessary in
embedded systems. Dual series termination is the least common scheme in the embedded memory
world.
• Parallel terminators should be placed close to the memories. Again, a dual parallel scenario can be
used, but in typical situations would be overkill for embedded applications.
• Always make sure the distance from the series terminator to the source output driver is much
shorter in length than the distance from the series terminator to the load (DDR memory).
• DDR2 series/parallel termination requires a VTT voltage supply. VTT is always half of the DDR2
memory voltage. In this example, VTT is 0.9 V for a 1.8-V DDR2 memory system.
• VREF must be supplied, as SSTL input buffers are differential in nature.
• Rs should be sized such that the output impedance of the driver plus the resistor is roughly the
same as the line impedance. On the MCF5445x, a starting point that produces good results is
22-Ω series resistors. Depending on the layer stack-up and material used, the desired size of Rs
can vary from less than 22 Ω to 33 Ω.
• RP is typically sized based on the drive currents used in the system. On the M54455EVB, 51-Ω
resistors were chosen. In DDR2 mode, the MCF5445x only supports one output drive level for
SSTL18 (SSTL18 is an SSTL pad at 1.8v).
• Differential clocks can be terminated with a single resistor between the two phases of the clock.
See Figure 6 for an example of this parallel termination scheme, which produces excellent clock
crossovers and reduces the number of components needed. One key item to consider is that all
DDR/DDR2 DIMMs include this single parallel terminator (between clock phases) on each DDR
DIMM module. If a design contains on-board DDR2 memories and a slot for a DDR2 DIMM
module, it is strongly recommended that a separate clock pair is routed to the on-board memories
and to the DDR/DDR2 DIMM.


In addition to this check...
**broken link removed**

Best of luck

 

[iliya24]

Thank you for your detailed help