blocking, non-blocking and if-else

Are non blocking assignments allowed in if-else statements in Verilog?
Can non blocking assignment statements be used inside if-else statements while to write this if-else statement inside a state of one state machine?

The choice between blocking and non-blocking assignments is a matter of programming style and functional intent. Learn the difference between the two assignments and the answers to your questions will become clear.

deve_59

I am aware between the differences of blocking and non-blocking.

The reason the thread was started is that if we see a book or tutorial of Verilog, the if-else statement is described with blocking assignments only. But if we see code of a d flipflop, we see that if-else being used with non blocking. So the code of a D flipflop contradicts with the if-else definition provided in a Verilog book or tutorial.

Can you also let me know if we should use blocking assignment in the if-else statement if we are using the if-else statement inside the always (*) block whereas this always (*) block is the part of a code of a state machine?

The choice between non-blocking or blocking assignment has nothing to do with it is being used inside or outside an if-else/case/for/while or any other procedural statement. The decision is soles based on the relationship between when the variable assignment happens, and when the variable is read.

Sequential logic should use non blocking while comibinatorial logic should use blocking. Simple rule to follow...

dave_59 said:

The choice between non-blocking or blocking assignment has nothing to do with it is being used inside or outside an if-else/case/for/while or any other procedural statement. The decision is soles based on the relationship between when the variable assignment happens, and when the variable is read.

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Can non-blocking statements be used inside if-else statements?

dave_59 said:

with it is being

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Can you please correct the grammar at the above quote so that the reply in understood better?

Can non-blocking statements be used inside if-else statements?

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Didn't dave_59 clearly answer the question?

As additional reading, see IEEE Std 1364.1, clause 5.2.2 Modeling edge-sensitive storage devices and the good old Cummings paper http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf

The choice between non-blocking assignment or blocking assignment has nothing to do with either assignment being used inside or outside an if-else/case/for/while or any other procedural statement.

FvM said:

Didn't dave_59 clearly answer the question?

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In one Verilog tutorial it was observed that the tutorial defines if-else statement with blocking assignments only and not with non blocking. This is a famous tutorial. In this tutorial the if-else statement definition does not include non blocking assignments.

As a result it is again asked for clarity that whether non-blocking statements can be used inside if-else or not. Please reply if you want to reply about it.

I am aware that when non blocking and blocking assignments should be used in design. The purpose here is to clarify the if-else definition. Id if-else definition also allows non-blocking statements then that tutorial has a mistake into it.
Regards

As a result it is again asked for clarity that whether non-blocking statements can be used inside if-else or not.

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The answer is of course "yes". But "can" doesn't tell about reasonability, about "should" or "should not". The said references discuss whether blocking or non-blocking assignments are appropriate in a specific context.

I guess, the tutorial has a reason to use blocking assignments in the examples you have read, e.g. because they are combinational always blocks or functions. You can't conclude that the tutorial is mistaken by omitting other cases.

If I wrote a Verilog tutorial, I would include examples of sequential always blocks with non-blocking assignments, e.g. if .. else constructs describing flip-flops and counters (as you find it in the quoted references).