Why not ?How can the synthesis tool infer the second blocking statement first and then the first blocking statement in the following code?
Verilog is a simulation language. The simulator will evaluate the expressions in the specified order. Synthesized hardware does everything in parallel. Again, if you try to draw the schematic of the design you will see that there is only one way to do it.By verilog construct it is said a blocking assignment is evaluated one after another.
As I mentioned earlier, the design is combinatorial, so the "sequential" evaluation only applies to the simulator.But I heard that synthesis tool is capable of obeying blocking nature of 'bloking statements'. In that case it should evaluate the sequentially and not in parallel as you wrote.
The synthesis tool will take the blocking nature into consideration as far it changes the synthesis result. I agree with std_match, that this isn't the case in the present example.But I heard that synthesis tool is capable of obeying blocking nature of 'bloking statements'. In that case it should evaluate the sequentially and not in parallel as you wrote.
What do you mean with "older value of temp". Remember, there is no register in the design. Without a register there is only one value for temp, the current value (c & d).Even to keep sequential nature of blocking statements, if I draw schematic, the temp input should get a feedback from putput to produce the older value of temp in the first line. Is not it?
always @(a or b or c or d or temp) begin
temp = a & b;
o = temp | c & d;
temp = a & !b;
end
always @(a or b or c or d or temp) begin
temp <= a & b;
o <= temp | c & d;
temp <= a & !b;
end
Strictly spoken, it's a tautology. It says, that in some cases the synthesis result will be different between blocking and non-blocking assignments. My example shows, that this happens with a real synthesis tool (Altera Quartus). I claim, that this result is according to the Verilog language rules and will be also observed in simulation.The synthesis tool will take the blocking nature into consideration as far it changes the synthesis result
They are evaluated sequentially, but the result is the same. As I already asked, which different result do you expect?I am not still getting how in my example in my first thread the blocking assignments are not evaluated sequentially by synthesis tool.
o = a & b | temp;
temp = c & d;
The second assignment comes to nothing. It's result isn't used in a succeeding term, because there's none. Of course, if you delete the first assignment, than the result of the second is remembered and used in the next delta cycle.Why cannot the second assignment win?
The synthesis is correct. As I mentioned earlier, if you get a mismatch with simulation, it it probably because you forgot to put temp in the sensitivity list.After evaluation of first bloking assignment the second assignment will be evaluated. So the synthesized net list should be such that it will be able to bring out the previous value of temp at the output 'o'. This is the way the simulator will work. So the synthesis tool since it pbeys bloking nature of verilog, it will also be able to match the simulation result.
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