ASIC_int
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How can the synthesis tool infer the second blocking statement first and then the first blocking statement in the following code?
module code2a (o, a, b, c, d);
output o;
input a, b, c, d;
reg o, temp;
always @(a or b or c or d) begin
o = a & b | temp;
temp = c & d;
end
endmodule
module code2a (o, a, b, c, d);
output o;
input a, b, c, d;
reg o, temp;
always @(a or b or c or d) begin
o = a & b | temp;
temp = c & d;
end
endmodule