BJT in PDK 0.18um, help me

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nguyenvanthien

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hi everybody!
i want to simulate bjt( pnp) in Cadence (PDK 0.18 um), can i find parameters it???. i don't know Vg0, Vbe0,... of PNP:?:.
Can you help me?:-o
thanks...
 

erikl, are you an expert about IC design???8-O
I'm very happy if you give me your mail address. I'm designing band gap. I want to ask you some problems.
look forward to your answer!:roll:
 

ok.
first, i think you know " the base-emitter voltage as a function of collector current and temperature:
Vbe= Vgo*( 1-T/To)+ Vbeo*(T/To)+(mkT/q)*ln(To/T)+(kT/q)*ln(Jc/Jco) "
To= 300K
Can you explain this function? How can i calculate constant Vgo, m by simulation of cadence?( they don't appear in pdk TSMC 0.18um). I want to use bjt PNP in band gap.
look forward your answer?
 

I don't know this equation. Where did you find it? What is Vgo?
 

it's in book analog integrated circuit design( ken.. martin). it's very important for designing band gap.
did you design band gap??? how did you do it?
look forward your answer!
 

nguyenvanthien said:
it's in book analog integrated circuit design( ken.. martin). it's very important for designing band gap.
did you design band gap??? how did you do it?
Click to expand...

Ok, I found it. Vgo is the bandgap voltage of silicon at 0K (≈ 1.2V). For the bandgap design I didn't need this equation: I just used a standard bandgap schematic. TempCo (~ 50ppm/K) was good enough for our requirement.
 

https://obrazki.elektroda.pl/6608223200_1383968299.png
https://obrazki.elektroda.pl/2422968900_1383968163.png
what do you think about these circuits?
I simulated in Cadence but results are very bad: Vout( from D of pmos M6) likes a line.
Can you point out my mistake? How can I improve it???

- - - Updated - - -

http://obrazki.elektroda.pl/6608223200_1383968299.png
http://obrazki.elektroda.pl/2422968900_1383968163.png
what do you think about these circuits?
I simulated in Cadence but results are very bad: Vout( from D of pmos M6) likes a line, it increses about 0.01v/ K, that's terrible.!
Can you point out my mistake? How can I improve it???
 

nguyenvanthien said:
... Vout( from D of pmos M6) likes a line, it increses about 0.01v/ K
Click to expand...

Sure, because these are PTAT current generation circuits, not bandgap designs.

BTW: your schematic is virtually illegible. I can't even discover M6 .
 

hi erikl,
I think i didn't design start up circuit.
You can read pdf file that i send in link. How you design startup circuit? How can I calculate start up circuit in Figure 23.27? I hope you explain it clearly for me.
I wait your answer!
thanks...
 

1. No permission to access this page!
2. A start-up circuit will not change the tempCo of your design!
 

I agree your second opinion.
But:
1/ I don't understand how calculate it for biasing in current mirror ( in my cadence design)?
2/ why do we have to have start- up???
look forward your answer!
 

Nguyen,

IMHO this forum is not the right place to teach you the basics of Analog Circuit Design, sorry! There are a lot of excellent books and free university courses available to study those subjects. Search these EDAboard analog forums or G00GLE and you can find them.

If you have concrete questions on concrete circuits, you may well come back and ask for help, but don't ask here for a personal free teacher.

Good luck! - erikl
 

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