Glendon J. Klassen
Newbie level 1
Hi there everyone,
I'm Glendon Klassen, Chief Operating Officer of bitEX Ltd. We specialize in cryptographic technologies, FPGA & ASIC design, PCB design, and novel networking solutions.
We're hosting a contest for anyone interested in:
-a one year paid internship with bitEX, with the possibility of a full-time job
-a Cyclone V GX SoC development board from Terasic
Contest Details:
The winner of the contest will be the person who has designed the "best" implementation of SHA-3 (Keccak) on FPGA.
Rules:
The "best" implementation will be determined as follows:
ALU consumption / clock speed = Score
The highest scorer (anyone who can match or beat our own proprietary implementation's speed, as well as that of other entrants) will be entitled to a one year paid internship with bitEX as well as the latest Cyclone V GX SoC development kit from Terasic. If there is no implementation that outperforms our own, the highest scoring contestant will be considered for employment and will still receive the Terasic board.
Submissions can be sent to glendon.klassen@bitex.co.uk as well in the following format:
-Email should include a short bio/CV
-Email should include a link to the .sof file for the SHA-3 implementation, since .sofs are usually too big to email.
Additionally, notice that you will be participating should be posted in the forum under this thread so we can keep track of entrants.
Contest details are subject to change without notice, but if you would like information at any point, please email glendon.klassen@bitex.co.uk or post right here.
We hope to hear from you all soon, and we thank you for your submissions. Let the games begin!
-Glendon
I'm Glendon Klassen, Chief Operating Officer of bitEX Ltd. We specialize in cryptographic technologies, FPGA & ASIC design, PCB design, and novel networking solutions.
We're hosting a contest for anyone interested in:
-a one year paid internship with bitEX, with the possibility of a full-time job
-a Cyclone V GX SoC development board from Terasic
Contest Details:
The winner of the contest will be the person who has designed the "best" implementation of SHA-3 (Keccak) on FPGA.
Rules:
- The SHA-3 implementation must be a 256-bit Keccak core.
- Designs must use only one core.
- Submissions must be written entirely in VHDL.
- Submissions must include JTAG probes; no serial/SPI/I2C/etc is required.
- Submissions may be in the form of .sof files in order to preserve the privacy of your code.
- Final products must be built for Altera low-density (Cyclone) FPGAs, though testing may be done using any vendor's chip.
- Clock speed may be altered by PLL, but implementations must work in both simulation and synthesis.
The "best" implementation will be determined as follows:
ALU consumption / clock speed = Score
The highest scorer (anyone who can match or beat our own proprietary implementation's speed, as well as that of other entrants) will be entitled to a one year paid internship with bitEX as well as the latest Cyclone V GX SoC development kit from Terasic. If there is no implementation that outperforms our own, the highest scoring contestant will be considered for employment and will still receive the Terasic board.
Submissions can be sent to glendon.klassen@bitex.co.uk as well in the following format:
-Email should include a short bio/CV
-Email should include a link to the .sof file for the SHA-3 implementation, since .sofs are usually too big to email.
Additionally, notice that you will be participating should be posted in the forum under this thread so we can keep track of entrants.
Contest details are subject to change without notice, but if you would like information at any point, please email glendon.klassen@bitex.co.uk or post right here.
We hope to hear from you all soon, and we thank you for your submissions. Let the games begin!
-Glendon
