Ashish Agrawal
Member level 3
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Hi,
I am having a memory (depth = 64, width = parameter) to be read fully and put it in a 1-D array (width = 64*memory data width). Only 1 row can be read at a time.
This is the verilog code I have written
I am getting an error during compilation related to constant parameter for following operations
(mem_addr + 1)*MEM_DATA_WIDTH and mem_addr *MEM_DATA_WIDTH
Can anyone tell me how to fix this error?
Thanks in advance.
I am having a memory (depth = 64, width = parameter) to be read fully and put it in a 1-D array (width = 64*memory data width). Only 1 row can be read at a time.
This is the verilog code I have written
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 parameter MEM_DATA_WIDTH = 32; localparam DATA_WIDTH_O = 64*MEM_DATA_WIDTH; reg [DATA_WIDTH_O -1 : 0] fsm_out; wire [MEM_DATA_WIDTH -1 :0] mem_data_i; reg [5:0] mem_addr; ///logic for generating mem_addr///// ////////////////////////////////////////// always @ * begin if (valid_i) fsm_out [(mem_addr + 1)*MEM_DATA_WIDTH -1 : mem_addr *MEM_DATA_WIDTH] <= mem_data_i; end
I am getting an error during compilation related to constant parameter for following operations
(mem_addr + 1)*MEM_DATA_WIDTH and mem_addr *MEM_DATA_WIDTH
Can anyone tell me how to fix this error?
Thanks in advance.
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