bit mirroring in verilog...

[davorin]

Is there an easy way of mirroring a bus signal in Verilog instead of using:

assign data_out = {data[0],data[1],data[2],data[3],.......};

 

[echo47]

In Verilog 2001 you can do this, but it's still not pretty:

module bitreverse (data, data_out);
  parameter bits = 16;
  input  [bits-1:0] data;
  output [bits-1:0] data_out;
  genvar g;

  generate for (g=0; g<bits; g=g+1) begin:bit
    assign data_out[g] = data[bits-1-g];
  end endgenerate
endmodule

 

[wkong_zhu]

reg[width-1:0] data_out;
always@(data) begin:reverse_bit
integer i;
for(i=0; i<width;i=i+1)
data_out = data[width-1-i];
end