bit flipping algorithm

[bunty_22]

hello

i need verilog hdl code for bitflipping algorithm
plzz help me out

 

[code_slave]

Specifics.

 

[D.A.(Tony)Stewart]

IBM invented the HIPO method of specs.

Hierarchical
Inputs
Processes
Outputs

Input =
Process = flip when ....
Output =


Not is a miscellaneous or logical operator .

 

[ads-ee]

Not is a miscellaneous or logical operator .

For VHDL NOT is an inversion operation, but in Verilog, which is what the OP wants, the logical operation is ! and the bitwise operator is ~.

I must say that any decent (well even that bad ones) tutorial will have that as one of the first things that is shown (Verilog operators).

 

[bunty_22]

the parity check matrix is 8*16;
well the input to encoder is 00001100..after encoding it is 1100100000001100;
the noise is 8 bit i.e 00000001
so these are d inputs
jus gimme an idea how to write d code

thanks

 

[K-J]

jus gimme an idea how to write d code

Get a text editor and start using it to write code rather than posting clueless posts.

 

[code_slave]

genvar i;
generate
for( i=0; i<length; i=i+1 )
begin :
if somevariable_bitposition
assign working = not working;
else
assign working = working;
endif
end
endgenerate

 

[ads-ee]

genvar i;
generate
for( i=0; i<length; i=i+1 )
begin :
if somevariable_bitposition
assign working = not working;
else
assign working = working;
endif
end
endgenerate

What is this not doing in the code not is a Verilog keyword for a NOT gate and has to be instantiated. Then you are using endif which is a VHDL keyword? Hmm, it can't be VHDL code as there is the assign statement which is a Verilog keyword and there is a genvar too!

Do you know either language or is this pseudo code where you're mixing languages to confuse the OP so they go away ;-).

 

[code_slave]

The rest of the post is missing.

There was a paragraph above the code section that included ' dis is d PSEUDO CODE' ,.
But it should be clear that it is 'PSEUDO'
'if somevariable_bitposition',
Obviously neither verilog/VHDL

Yep, there is a mixture, I had two projects open , VHDL/ Vlog , debugging an FPGA SATA interface with a broken JTag Cable which requires a finger, plus I was dealing with a SF-Express and an aliexpress seller on chat..

The rest of my post is obviously included in the cut & paste to Ali-express……

 

[mrflibble]

The rest of my post is obviously included in the cut & paste to Ali-express……

Good thing then that it doesn't make too much of a difference. It's always a surprise what you are going to get this time, no matter what you specify to the seller. ;-)

 

[code_slave]

Yes,
That's why I sit on these guys…..

In reality I know FS-express scans at collection within 10 minutes, they show scanning yesterday (13th), 4 days AFTER seller stated them as shipped.(It's 1-2 day delivery to H.K)
I need these silicon sheets to get a bigger heatsink on the FPGA, it's starting to smell, short some place……