flote21
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Code Verilog - [expand]
Do you even understand what you just asked?But the problem is that with that solution I can't ouput data every clock after the pipeline delay... I need one solution to ouput data every clock without "deadtimes" in the output...Any idea?
Do you even understand what you just asked?
How are you supposed to output data on every clock when the binning involves adding 5 pixels together, when you only get 4 pixels every clock? Unless you were supposed to do some sort of running sum...(i.e. d1+d2+d3+d4+d5, d2+d3+d4+d5+d6, d3+d4+d5+d6+d7, etc) then you could compute it on every clock.
If your original algorithm is correct and you have to output bin data on every clock then you will have to output on a clock that is 4/5 the input clock frequency and use a FIFO to ensure you don't under/overflow the binned pixel output.
Regards
- - - Updated - - -
BTW, the implementation you proposed will use a lot more adders and will also be much slower as your implementation requires that the 3 additions in the first case are done in 1 clock cycle. If you implemented what I showed you and follow it by a pipelined adder you would use fewer adders and it could run at a much higher frequency.
Only if you are sticking to your requirement that you output binned pixels on each clock...the aggregate rate for output bins is 4/5 your input clock that sends you 4 pixels per clock.Why I need to use a FIFO to ensure you don't under/overflow the binned pixel output??
This doesn't make any sense based on your original request.I can binning the incomming pixels on the fly! but the problem of this solution is that I have output freq limitation. The pixels are incomming at 148.5 MHz and I need to output binning pixels at maximum 500Hz. But it does not work. The maximum frequency that I can set up is 350 Hz. And I think that my pipeline algorithm is limiting in any way the output frequency.
Code VHDL - [expand]
I think you need to supply the testbench that you are using to test this entity/architecture. It's hard to determine what your input protocol would look like.
Like I said before your implementation choice uses a lot of adders, which would reduce to a single 5 pixel adder tree, if you performed the translation of 4 pixels to 5 pixels as I originally suggested.
It shouldn't be hard to translate what I posted to VHDL as there isn't anything complicated in the case statement. The case statement just translates the table above it.
The pixels are pipelined delayed so you have access to both the most recent pixel and the previous set of pixels. That gives you access to all 5 pixels you need for each bin.
Do your calculations include the Ethernet framing overhead? It doesn't look like it as you aren't adding amything else to the raw pixel data.
variable temp : unsigned(w+8 downto 0);
temp := d_in * 206;
d_out <= temp(w+8 downto 8);Okay, I see the 700 Mbps is the maximum Ethernet payload rate, that wasn't clearly stated. 700Mbps is kind of low for Gigabit Ethernet, you must have rather short Ethernet packets.Yes In the maximum ETH frame rate (700 Mbps) is already included.
---------------------------
entity ETH_TX_CTRL is
---------------------------
port (
FIFO_WR_FUL_ERR : out std_logic; -- Fifo WR Full Error
FIFO_RD_FUL_ERR : out std_logic; -- Fifo RD Full Error
-- Clock and Reset
CLK : in std_logic; -- Module Clock
RST : in std_logic; -- Module Reset (Asynch Active high)
RUN : in std_logic; -- Run
-- Video Stream
VIDEO_XSIZE : in std_logic_vector(11 downto 0); -- Video X Size
VIDEO_YSIZE : in std_logic_vector(11 downto 0); -- Video Y Size
VIDEO_SOI : in std_logic; -- Video Start of Image
VIDEO_DAV : in std_logic; -- Video Data Valid
VIDEO_DATA : in std_logic_vector(63 downto 0); -- Video Data
VIDEO_EOI : in std_logic; -- Video End of Image
-- uC Data Interface, to insert inside TX Video Frames
UC_TX_DAV : in std_logic; -- uC New Data to Send
UC_TX_DATA : in std_logic_vector(23 downto 0); -- uC New Data
-- Encryption
ENCRYPT_IN : in std_logic_vector(31 downto 0); -- Encrypt Value to send in the Ethernet Frames
-- GEDEK Interface
ETH_TXREADY : in std_logic; -- Ethernet Tx Ready ('0' = not ready !)
ETH_TXSOP : out std_logic; -- Ethernet Tx Start of Packet
ETH_TXDAV : out std_logic; -- Ethernet Tx Data Valid
ETH_TXDATA : out std_logic_vector(31 downto 0); -- Ethernet Tx Data
ETH_TXEOP : out std_logic -- Ethernet Tx End of Packet
);
---------------------------
end entity ETH_TX_CTRL;
---------------------------
------------------------------------
architecture RTL of ETH_TX_CTRL is
------------------------------------
-- --------------------------
-- Altera Single Clock FIFO
-- --------------------------
component SCFIFO is
generic (
ADD_RAM_OUTPUT_REGISTER : string;
INTENDED_DEVICE_FAMILY : string;
LPM_NUMWORDS : natural;
LPM_SHOWAHEAD : string;
LPM_TYPE : string;
LPM_WIDTH : natural;
LPM_WIDTHU : natural;
OVERFLOW_CHECKING : string;
UNDERFLOW_CHECKING : string;
USE_EAB : string
);
port (
ACLR : in std_logic ;
CLOCK : in std_logic ;
SCLR : in std_logic ;
WRREQ : in std_logic ;
DATA : in std_logic_vector(LPM_WIDTH -1 downto 0);
FULL : out std_logic ;
USEDW : out std_logic_vector(LPM_WIDTHU-1 downto 0);
EMPTY : out std_logic ;
RDREQ : in std_logic ;
Q : out std_logic_vector(LPM_WIDTH -1 downto 0)
);
end component SCFIFO;
constant RESOLUTION_X : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(48, 16));
constant RESOLUTION_Y : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(96, 16));
-- FIFO to store Video Data
constant FIFO_DEPTH : positive := 10;
constant FIFO_WSIZE : positive := 64;
signal FIFO_CLR : std_logic;
signal FIFO_WR : std_logic;
signal FIFO_IN : std_logic_vector(FIFO_WSIZE-1 downto 0);
signal FIFO_FUL : std_logic;
signal FIFO_NB : std_logic_vector(FIFO_DEPTH-1 downto 0);
signal FIFO_EMP : std_logic;
signal FIFO_RD : std_logic;
signal FIFO_OUT : std_logic_vector(FIFO_WSIZE-1 downto 0);
signal FIFO_RDSEL : std_logic;
-- FIFO to store uC Data
constant UC_FIFO_DEPTH : positive := 8;
constant UC_FIFO_WSIZE : positive := 32;
signal UC_FIFO_CLR : std_logic;
signal UC_FIFO_WR : std_logic;
signal UC_FIFO_IN : std_logic_vector(UC_FIFO_WSIZE-1 downto 0);
signal UC_FIFO_FUL : std_logic;
signal UC_FIFO_NB : std_logic_vector(UC_FIFO_DEPTH-1 downto 0);
signal UC_FIFO_EMP : std_logic;
signal UC_FIFO_RD : std_logic;
signal UC_FIFO_OUT : std_logic_vector(UC_FIFO_WSIZE-1 downto 0);
signal UC_PACK_CNT : unsigned(15 downto 0);
signal VIDEO_RUN : std_logic;
signal VIDEO_SOIm : std_logic;
signal VIDEO_EOIm : std_logic;
signal FRAME_CNT : unsigned(31 downto 0);
constant ETH_TXSIZE : positive := 361; -- 3 UDP Headers + 358 x 32bits words Data : max optimal value
type ETH_TXFSM_t is ( s_IDLE, s_SEND_INFO_1, s_SEND_INFO_2, s_SEND_INFO_3, s_SEND_DATA, s_SEND_EOP );
signal ETH_TXFSM : ETH_TXFSM_t;
signal ETH_TXEND : std_logic;
signal ETH_TXCNT : integer range 0 to ETH_TXSIZE;
--------
begin
--------
-- -------------------------------
-- VIDEO DATA FIFO
-- -------------------------------
FIFO_CLR <= VIDEO_SOI or not RUN;
FIFO_WR <= VIDEO_DAV and VIDEO_RUN;
FIFO_IN <= VIDEO_DATA;
-- FIFO to store incoming data to send to GEDEK
-- Perform 64bits to 32bits conversion !
i_VIDEO_FIFO : SCFIFO
generic map (
ADD_RAM_OUTPUT_REGISTER => "ON",
INTENDED_DEVICE_FAMILY => "Cyclone IV",
LPM_NUMWORDS => 2**FIFO_DEPTH,
LPM_SHOWAHEAD => "ON",
LPM_TYPE => "SCFIFO",
LPM_WIDTH => FIFO_WSIZE,
LPM_WIDTHU => FIFO_DEPTH,
OVERFLOW_CHECKING => "ON",
UNDERFLOW_CHECKING => "ON",
USE_EAB => "ON"
)
port map (
ACLR => RST ,
CLOCK => CLK ,
SCLR => FIFO_CLR,
WRREQ => FIFO_WR ,
DATA => FIFO_IN ,
FULL => FIFO_FUL,
USEDW => FIFO_NB ,
EMPTY => FIFO_EMP,
RDREQ => FIFO_RD ,
Q => FIFO_OUT
);
FIFO_RD <= ETH_TXREADY and not FIFO_EMP and FIFO_RDSEL when ETH_TXFSM = s_SEND_DATA else '0';
-- FIFO Full Error Detection
process(CLK, RST)
begin
if RST = '1' then
FIFO_WR_FUL_ERR <= '0';
elsif rising_edge(CLK) then
if FIFO_FUL = '1' and FIFO_WR = '1' then
FIFO_WR_FUL_ERR <= '1';
end if;
end if;
end process;
process(CLK, RST)
begin
if RST = '1' then
FIFO_RD_FUL_ERR <= '0';
elsif rising_edge(CLK) then
if FIFO_EMP = '1' and FIFO_RD = '1' then
FIFO_RD_FUL_ERR <= '1';
end if;
end if;
end process;
-- FIFO assertions
process
begin
wait until rising_edge(CLK);
assert not (FIFO_EMP = '1' and FIFO_RD = '1')
report "[ETH_TX_CTRL] Try to read while FIFO is empty !" severity failure;
assert not (FIFO_FUL = '1' and FIFO_WR = '1')
report "[ETH_TX_CTRL] Write in FIFO Full !" severity failure;
end process;
-- -------------------------------
-- uC DATA FIFO
-- -------------------------------
UC_FIFO_CLR <= not RUN;
UC_FIFO_WR <= UC_TX_DAV and VIDEO_RUN;
UC_FIFO_IN <= x"00" & UC_TX_DATA;
-- FIFO to store incoming data from GEDEK
-- FIFO 1024x32bits, Show Ahead Mode, Output registered
i_UC_FIFO : SCFIFO
generic map (
ADD_RAM_OUTPUT_REGISTER => "ON",
INTENDED_DEVICE_FAMILY => "Cyclone IV",
LPM_NUMWORDS => 2**UC_FIFO_DEPTH,
LPM_SHOWAHEAD => "ON",
LPM_TYPE => "SCFIFO",
LPM_WIDTH => UC_FIFO_WSIZE,
LPM_WIDTHU => UC_FIFO_DEPTH,
OVERFLOW_CHECKING => "ON",
UNDERFLOW_CHECKING => "ON",
USE_EAB => "ON"
)
port map (
ACLR => RST ,
CLOCK => CLK ,
SCLR => UC_FIFO_CLR,
WRREQ => UC_FIFO_WR ,
DATA => UC_FIFO_IN ,
FULL => UC_FIFO_FUL,
USEDW => UC_FIFO_NB ,
EMPTY => UC_FIFO_EMP,
RDREQ => UC_FIFO_RD ,
Q => UC_FIFO_OUT
);
-- uC FIFO assertions
process
begin
wait until rising_edge(CLK);
assert not (UC_FIFO_EMP = '1' and UC_FIFO_RD = '1')
report "[ETH_TX_CTRL] Try to read while UC_FIFO is empty !" severity failure;
assert not (UC_FIFO_FUL = '1'and UC_FIFO_WR = '1')
report "[ETH_TX_CTRL] Write in UC_FIFO Full !" severity failure;
end process;
-- -------------------
-- TX FRAME MANAGEMENT
-- -------------------
TX_proc : process(RST,CLK)
begin
if RST='1' then
ETH_TXEND <= '0';
ETH_TXSOP <= '0';
ETH_TXEOP <= '0';
ETH_TXDAV <= '0';
ETH_TXDATA <= (others => '0');
ETH_TXCNT <= 0 ;
ETH_TXFSM <= s_IDLE;
FRAME_CNT <= (others => '0');
VIDEO_RUN <= '0';
VIDEO_SOIm <= '0';
VIDEO_EOIm <= '0';
UC_PACK_CNT <= (others=>'0');
UC_FIFO_RD <= '0';
FIFO_RDSEL <= '0';
elsif rising_edge(CLK) then
UC_FIFO_RD <= '0';
-- Latch Run Signals at Start of Frame
if RUN = '0' then
VIDEO_RUN <= '0';
elsif VIDEO_SOI = '1' then
VIDEO_RUN <= RUN;
end if;
-- Memorize Start / End of Image Flags
VIDEO_SOIm <= (VIDEO_SOIm or VIDEO_SOI) and RUN;
VIDEO_EOIm <= (VIDEO_EOIm or VIDEO_EOI) and VIDEO_RUN;
case ETH_TXFSM is
-- Idle State : waiting for :
-- * Enough data to send in the Fifo ?
-- * End of Image flag from Video Interface
when s_IDLE =>
ETH_TXSOP <= '0';
ETH_TXEOP <= '0';
ETH_TXDAV <= '0';
ETH_TXEND <= '0';
-- Enough Words in FIFO
if unsigned(FIFO_NB)*2 >= ETH_TXSIZE-3 then
ETH_TXCNT <= ETH_TXSIZE-3; -- Load Number of Data to send
ETH_TXFSM <= s_SEND_INFO_1; -- Go Send UDP Header
-- End of Image !
elsif VIDEO_EOIm = '1' then
ETH_TXEND <= '1'; -- will be used to clear the EOIm
ETH_TXCNT <= to_integer(unsigned(FIFO_NB))*2; -- Load Number of Data to send
ETH_TXFSM <= s_SEND_INFO_1; -- Go Send UDP Header
end if;
-- UDP Header Word 1 :
-- * if First Frame for the Image, send the Resolution
-- * else send the Packets Counter on 16 MSBs
when s_SEND_INFO_1 =>
-- Send the SOP of this frame
ETH_TXSOP <= '1';
ETH_TXDAV <= '1';
if VIDEO_SOIm = '1' then -- New Image
ETH_TXDATA <= x"0" & VIDEO_YSIZE & x"0" & VIDEO_XSIZE;
UC_PACK_CNT <= (others => '0'); -- Reset Packets counter
else
ETH_TXDATA <= x"0000" & std_logic_vector(UC_PACK_CNT);
UC_PACK_CNT <= UC_PACK_CNT + 1; -- Increment for next time
end if;
ETH_TXFSM <= s_SEND_INFO_2;
-- UDP Header Word 2 : Video Frame Counter
when s_SEND_INFO_2 =>
if ETH_TXREADY = '1' then -- SOP accepted
ETH_TXSOP <= '0'; -- release the SOP
ETH_TXDAV <= '1'; -- send 2nd data
ETH_TXDATA <= std_logic_vector(FRAME_CNT);
ETH_TXFSM <= s_SEND_INFO_3;
end if;
-- UDP Header Word 3 :
-- * if First Frame for the Image, send the Encryption Word
-- * else send the uC Word (if anything to send)
-- * else 0's
when s_SEND_INFO_3 =>
if ETH_TXREADY = '1' then -- 2nd data accepted
ETH_TXDAV <= '1';
if VIDEO_SOIm = '1' then
ETH_TXDATA <= ENCRYPT_IN; -- Encryption Word
else
-- Something to Send on the Dedicated uC Word in UDP Header ?
if UC_FIFO_EMP = '0' then -- Yes (uC has sent something to the FPGA)
UC_FIFO_RD <= '1'; -- Read the word now so that it will be available after
ETH_TXDATA <= UC_FIFO_OUT; -- uC Word
else
ETH_TXDATA <= (others => '0'); -- All Zeros
end if;
end if;
VIDEO_SOIm <= '0'; -- Clear the Start of Image flag now
FIFO_RDSEL <= '0';
ETH_TXFSM <= s_SEND_DATA;
end if;
-- Sending Data
when s_SEND_DATA =>
ETH_TXDAV <= '1';
if FIFO_RD = '1' then
ETH_TXDATA <= FIFO_OUT(63 downto 32);
elsif FIFO_EMP = '0' and FIFO_RDSEL = '0' then
ETH_TXDATA <= FIFO_OUT(31 downto 00);
end if;
if ETH_TXREADY = '1' then -- Data Acknowledge by GEDEK
FIFO_RDSEL <= not FIFO_RDSEL;
if ETH_TXCNT = 1 then
ETH_TXEOP <= '1';
ETH_TXFSM <= s_SEND_EOP;
-- Clear the EOIm only if it was really the last frame to send
if VIDEO_EOIm = '1' and ETH_TXEND = '1' then
FRAME_CNT <= FRAME_CNT + 1;
VIDEO_EOIm <= '0'; -- Clear the End of Image flag now
end if;
end if;
ETH_TXCNT <= ETH_TXCNT - 1;
end if;
-- Sending EOP
when s_SEND_EOP =>
if ETH_TXREADY = '1' then
ETH_TXDAV <= '0'; -- release the DAV
ETH_TXEOP <= '0'; -- release the EOP
ETH_TXFSM <= s_IDLE;
end if;
end case;
end if;
end process TX_proc;
-----------------------
end architecture RTL;
-----------------------One thing you should check in a simulation or in the signaltap is monitor the UC_FIFO_NB used count and see how it behaves. I suspect you will discover the count fluctuates in such a way that the FIFO is going empty due to bursting when packets are sent. UDP has a pretty low overhead so you should easily be able to send 700Mbps.
I suggest running for many packets to see the overall trend of the FIFO level as it runs. You may not have run enough packets to see what is happening. Setting the UC_FIFO_NB count to an unsigned analog display in Modelsim, will give you a nice view of what is going on.
Hi,
I have already found problem!!! I was losing pixel and frames due to the PEAK the Bandwidth of the Ethernet side. This is the equation to handle this stuff:
For example, given a RealFrame = 1920 pixels x 219 lines. Aftter doing an Horizontal binning of 5 (Adding 5 pixels together) => BinnedFrame = 1920/5 x 219 = 384x219.
If I want to run the system at frame_rate = 500Hz => LineTime=219/500=9.13uS. But during a complete line I have to send 384x16bits=6144bits. So we have to send in average 6144bits in 9.13 uS => BW_ETH=672.94Mbps. Very close to the 700Mbps which is the limitation of my ETH interface....
This is a limitation of the system so I can't do any more here.
Thanks anyway for your interest and help. Thanks a lot dude!!!
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