delon
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I am writing a systemverilog cover group for my VHDL IP. My plan is to write a separate SV code where I assume that I have access to the internal signals of my VHDL ip. Afterwards, I will just do a bind so that the SV segment of code get automatically instantiated in VHDL by the simulator. Please correct me if I am wrong. I never used binding before.
Before I start off, I was trying to see how binding works and wrote a small program to test it. Here it is...
test_bind.sv
Now, when I try to compile it, I get the following error:
my_vhdl_module is the simple vhdl src code. I also tried the same with a very simple verilg counterpart of my_vhdl_module but getting the same error. I feel stupid as it looks like a simple bug but I just couldn't figure it out yet. Any comment on this will be really helpful.
Before I start off, I was trying to see how binding works and wrote a small program to test it. Here it is...
test_bind.sv
Code:
module test_bind(input clk, input enable);
initial @(posedge clk) $display("binding worked!!");
endmodule
bind my_vhdl_module test_bind instance_test_bind(clk, enable);Now, when I try to compile it, I get the following error:
Code:
Following verilog source has syntax error :
"test_bind.sv", 5: token is 'test_bind'
bind my_vhdl_module test_bind instance_test_bind(clk, enable);
^
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