ibubhai
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Hi, I am facing problem in binding the bit blasted signal of the netlist to the corresponding bussed signal in the vera interface. Can anyone suggest how to bind such bit blasted signals. I am not looking for making any kind of wrapper.
interface vera_if {
input [31:0] data INPUT_PORT hdl_node "/test_bench/dut/netlist/\data";
}
here data is bit blasted in the netlist as \data[0]........\data[31]
Thanks
interface vera_if {
input [31:0] data INPUT_PORT hdl_node "/test_bench/dut/netlist/\data";
}
here data is bit blasted in the netlist as \data[0]........\data[31]
Thanks