Biestable D in VHDL TestBech 1

Status
Not open for further replies.
I

Ivaylo Plamenov

Newbie level 3
Joined
Feb 11, 2013
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,309
Please someone can make help me with TestBech of Flip-flop D with this entity and architecture :

LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
ENTITY BiestableD IS
PORT ( D, CLK : IN std_logic;
rstH : IN std_logic;
Q : OUT std_logic);
END BiestableD ;

ARCHITECTURE BiestableDarq OF BiestableD IS
BEGIN
PROCESS (CLK, rstH)
BEGIN
IF (rstH = ‘1’) THEN
Q <= ‘0’;
ELSIF (CLK’event and CLK = ‘1’) THEN
Q <= D;
END IF;
END PROCESS;
END BiestableDarq;

Thank´s !!!
 

LIBRARY ieee;
USE ieee . STD_LOGIC_1164.ALL;

ENTITY test_biestable IS END test_biestable;
ARCHITECTURA test_1 OF test_biestable IS
COMPONENT BiestableD IS
PORT ( D, CLK : IN std_logic;
rstH : IN std_logci;
Q : OUT std_logic);
END COMPONENT;
FOR C1: BiestableD USE ENTITY Word, BiestableD;
SIGNAL D, CLK, rstH, Q: std_logic;
BEGIN
C1: BiestableD PORT MAP (D => D, CLK => CLK, rstH => rstH, Q =>Q);
rstH <=’1’, ‘0’ AFTER 50ns;
Q <= ‘0’, ‘1’ AFTER 20ns;
D <= ‘0’, ‘1’ AFTER 20ns;
CLK <= ‘0’;
PROCESS (CLK)
BEGIN
CLK <= NOT CLK AFTER 20ns;
END PROCESS;
END TEST_1;

My teacher told me that I have got some fail :/
 

1) "rstH:IN std_logci"===> logic
2) I think you need to put your stimulus inside a process
3) You need to assign an initial value to CLK
4) You can't have a sensitivity list("PROCESS(CLK)") and AFTER statements in a process; one or the other.
 

I do this: LIBRARY ieee;
USE ieee . STD_LOGIC_1164.ALL;

ENTITY test_biestable IS END test_biestable;
ARCHITECTURA test_1 OF test_biestable IS
COMPONENT BiestableD IS
PORT ( D, CLK : IN std_logic;
rstH : IN std_logci;
Q : OUT std_logic);
END COMPONENT;
FOR C1: BiestableD USE ENTITY Word, BiestableD;
SIGNAL D, CLK, rstH, Q: std_logic;
BEGIN
C1: BiestableD PORT MAP (D => D, CLK => CLK, rstH => rstH, Q =>Q);
rstH <=’1’, ‘0’ AFTER 50ns;
Q <= ‘0’, ‘1’ AFTER 20ns;
D <= ‘0’, ‘1’ AFTER 20ns;
CLK <= ‘0’;
PROCESS (CLK)
BEGIN
CLK <= NOT CLK AFTER 20ns;
END PROCESS;
END TEST_1;

but i cant understand that i can´t have a sensitivity list ("PROCESS(CLK)") and AFTER statements in a process :/
 

Ivaylo Plamenov said:
but i cant understand that i can´t have a sensitivity list ("PROCESS(CLK)") and AFTER statements in a process :/
Click to expand...
I might have been wrong; you can't use a WAIT statement with a sensitivity list. Perhaps you CAN use a sensitivity list and AFTER, but why would you?

And you're assigning a value to Q, which is an OUTPUT.
 
Last edited:

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…