In most cases these things have to be custom built, Altera Megafunactions (ALTLVDS_RX and ALTLVDS_TX) can be used to realize what you want. Quartus will generate the VHDL code from the block diagram you construct using these Megafuctions. HTH.
module test(in1,in2,oe,out,bidir,bidir_n);
input in1;
input in2;
input oe;
inout bidir;
inout bidir_n;
output out;
wire tmp1;
and(tmp1,in1,in2);
ALT_IOBUF_DIFF inst(
.i(tmp1),
.oe(oe),
.o(out),
.io(bidir),
.iobar(bidir_n)
);
defparam inst.io_standard = "LVDS";
defparam inst.current_strength = "12mA";
endmodule
Error: Current Strength logic option is set to 12mA for pin bidir, but setting is not supported by I/O standard LVDS
In most cases these things have to be custom built, Altera Megafunactions (ALTLVDS_RX and ALTLVDS_TX) can be used to realize what you want. Quartus will generate the VHDL code from the block diagram you construct using these Megafuctions. HTH.
module Bi_dir_bus (data_to_from_bus, send_data, rcv_data);
inout [15: 0] data_to_from_bus;
input send_data, rcv_data;
wire [15: 0] ckt_to_bus;
wire [15: 0] data_to_trom_bus, data_from_bus;
assign data_from_bus = (rcv_data) ? data_to_from_bus : 16'bz;
assign data_to_from_bus = (send_data) ? ckt_to_bus : data_to_trom_bus;
endmodule
Error: Bidirectional pin data_to_from_bus[0] with a pseudo-differential I/O standard must use the output enable control signal on the output buffer
While developing the folowing design in Verilog for Cyclone III
Code:module Bi_dir_bus (data_to_from_bus, send_data, rcv_data); inout [15: 0] data_to_from_bus; input send_data, rcv_data; wire [15: 0] ckt_to_bus; wire [15: 0] data_to_trom_bus, data_from_bus; assign data_from_bus = (rcv_data) ? data_to_from_bus : 16'bz; assign data_to_from_bus = (send_data) ? ckt_to_bus : data_to_trom_bus; endmodule
receive the error
when I try to use BLVDS I/O standart for "data_to_from_bus".
What is the way to solve that problem?
assign data_to_from_bus = (send_data) ? ckt_to_bus : data_to_trom_bus;
...
inout bidir_pin,
...
wire direction;
wire signal_out;
wire signal_in;
// using bidir_pin as an output.
assign bidir_pin = direction ? signal_out : 1'bz;
// using the bidir_pin as an input.
assign signal_in = bidir_pin;
Error: Bidirectional pin bidir_pin with a pseudo-differential I/O standard must use the output enable control signal on the output buffer
bidir_pin
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 library ieee; use ieee.std_logic_1164.all; LIBRARY cycloneiii; USE cycloneiii.all; entity blvds_test2 is port ( b : inout std_logic; b_bar : inout std_logic; bi : in std_logic; be : in std_logic; bo : out std_logic ); end entity; architecture rtl of blvds_test2 is COMPONENT cycloneiii_io_ibuf GENERIC ( bus_hold : STRING := "false"; differential_mode : STRING := "false"; simulate_z_as : STRING := "Z"; lpm_type : STRING := "cycloneiii_io_ibuf" ); PORT ( i : IN STD_LOGIC := '0'; ibar : IN STD_LOGIC := '0'; o : OUT STD_LOGIC ); END COMPONENT; COMPONENT cycloneiii_io_obuf GENERIC ( bus_hold : STRING := "false"; open_drain_output : STRING := "false"; lpm_type : STRING := "cycloneiii_io_obuf" ); PORT ( i : IN STD_LOGIC := '0'; o : OUT STD_LOGIC; obar : OUT STD_LOGIC; oe : IN STD_LOGIC := '1'; seriesterminationcontrol : IN STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0') ); END COMPONENT; COMPONENT cycloneiii_pseudo_diff_out PORT ( i : IN STD_LOGIC := '0'; o : OUT STD_LOGIC; obar : OUT STD_LOGIC ); END COMPONENT; signal b_wire : std_logic; signal b_bar_wire : std_logic; begin ibufa : cycloneiii_io_ibuf GENERIC MAP ( bus_hold => "false", differential_mode => "true" ) PORT MAP ( i => b, ibar => b_bar, o => bo ); obuf_ba : cycloneiii_io_obuf GENERIC MAP ( bus_hold => "false", open_drain_output => "false" ) PORT MAP ( i => b_bar_wire, o => b_bar, oe => be ); obufa : cycloneiii_io_obuf GENERIC MAP ( bus_hold => "false", open_drain_output => "false" ) PORT MAP ( i => b_wire, o => b, oe => be ); pseudo_diffa : cycloneiii_pseudo_diff_out PORT MAP ( i => bi, o => b_wire, obar => b_bar_wire ); end rtl;
module starter_3 (led_5, led_6, clk_2 /*25 MHz*/,
out, out_n);
reg trans, trans_n;
output out, out_n;
reg T_5;
reg [25:0] COUNT_clk_2;
output reg led_5, led_6;
input wire clk_2;
ALT_OUTBUF_DIFF inst1(
.i(T_5), //indicates with led_5
.o(out),
.obar(out_n)
);
defparam inst1.io_standard = "LVDS";
defparam inst1.weak_pull_up_resistor = "off";
defparam inst1.enable_bus_hold = "off";
ALT_INBUF_DIFF inst2(
.i(trans),
.ibar(trans_n),
.o(inp_dif_2) // indicates with led_6
);
defparam inst2.io_standard = "LVDS";
defparam inst2.weak_pull_up_resistor = "off";
defparam inst2.enable_bus_hold = "off";
initial
begin
T_5<=0;
COUNT_clk_2<=0;
end
always @(posedge clk_2)
begin
COUNT_clk_2<=(COUNT_clk_2+1'b1);
if (COUNT_clk_2[25]==1)
begin
COUNT_clk_2<=0;
T_5<=!T_5;
end
end
always @(inp_dif_2)
begin
led_6<=!led_6;
end
always @(negedge T_5)
begin
led_5<=!led_5;
end
always @(out)
begin
trans<=out;
trans_n<=out_n;
end
endmodule
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 // so this.... ALT_OUTBUF_DIFF inst1( .i(T_5), //indicates with led_5 .o(out), .obar(out_n) ); defparam inst1.io_standard = "LVDS"; defparam inst1.weak_pull_up_resistor = "off"; defparam inst1.enable_bus_hold = "off"; // becomes this... ALT_OUTBUF_DIFF #( .io_standard ("LVDS"), .weak_pull_up_resistor ("off"), .enable_bus_hold ("off") ) inst1 ( .i (T_5), //indicates with led_5 .o (out), .obar (out_n) );
-- was experimentally checked if always @(*) works more properly than always @(out), with a negative result. Moreover, I don't catch a thing, why I should add sensitivity of changing out_n in always if out_n and out are changing simultaneously?Also you are not using always @(*) but are using always @(dout)
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