Biasing two stage amplifier

[anhnha]

Please help me with the question below about two stage amplifier. Thank you.

Here is the reference lecture: **broken link removed**

 

[LvW]

Well, I am not a specialist for designing such a circuit - and to ANALYZE/VERIFY a circuit that was designed by somebody else always is not easy, however I will try to give some comments:
* Transistors M1 and M2 are biased with a corresponding DC voltage at its gate nodes. Razavi calls this voltage "common mode voltage" because it must be the same for both transistors. Hence, this voltage Vin,CM must exceed a certain limit - and that is the reason for the left part of the last inequation.
* I think, biasing of M4 and M6 is explained in the text (points 2..5).
* Question: Does Razavi give some explanations how to arrive at the right side of the inequation?

 

[anhnha]

Thank you.
For the differential pair with resistive load, the common mode voltage is explained well in the book.
Here is an excerpt from the book.

However, I got stuck with the calculation of common mode voltage for M1 and M2 above of the differential pair with active load (current mirror).
The lower limit of common mode voltage is still same as the resistive load. However, what is the upper limit? There is not resistor there. If we see current source as a component with infinite resistor than the upper limit will be zero. That is really confusing.

 

[anhnha]

I think I figured out the upper limit for common mode voltage here.
It is VDD - VGS3 + VTH.
VGS3 here is a constant because M3 is in saturation and the current flowing it is I5/2 = const.
Could you explain why we connect D and G of M3 together? I think it is to make sure that M3 will be in saturation. However, that make the circuit no longer symmetric.
For example, if the G and D of M3 isn't connected together, can we also make them in saturation by choosing an appropriate common mode voltage for M1 and M2?

 

[tompham]

Hi anhnha
You can do upper limit as below:

Condition for M1 : Vds1 >= Vdsat1 = Vgs1 - Vtn
=> Vd1 >= Vg1 - Vtn
Or Vg1 <= Vd1 + Vtn
Vg1 <= VDD - Vsg3 + Vtn
Vg1 <= VDD - (Vdsat3 + Vtp) + Vtn
=> Upper limit Vin <= VDD - (Vdsat3 + Vtp) + Vtn

 

[anhnha]

Hi Tom.
Thank you for the reply.
I followed you and understood up to this.
Vg1 <= VDD - Vsg3 + Vtn
However, could you explain why you replace Vsg3 = Vdsat3 + Vtp?
Is Vdsat3 given?
I prefer to use Vsg3 because I know for certain that it is a constant. I can calculate it from the equation.
I5/2 = k(Vsg3 - Vtp)^2

And could you explain how to force M6 to be in saturation?

 

[tompham]

Hi anhnha

condition for a transistor in SATURATION: vds >= vdsat
Since vdsat = vgs - vt
=====> vgs = vdsat + vt
======> vgs3 = vdsat3 + vt
Note : M3 in diode connection mean in SATURATION

 

[anhnha]

Hi Tom.

I understand that condition. However, I was wondering why don't you just write the condition for the upper limit Vg1 <= VDD - Vsg3 + Vtn instead of Vg1 <= VDD - (Vdsat3 + Vtp) + Vtn?

1. Vg1 <= VDD - Vsg3 + Vtn
2. Vg1 <= VDD - (Vdsat3 + Vtp) + Vtn

I know that #1 and #2 are equivalent but is it clear that with #2 we need more calculation?
With #1, we only need to calculate Vsg3 from the equation I5/2 = k(Vsg3 - Vtp)^2
With #2, we had to do more calculation.
First we need to calculate Vsg3 the equation I5/2 = k(Vsg3 - Vtp)^2

BTW, could you explain how to force M6 to be in saturation?
Then we need to calculate vsg3= Vdsat3 + vtp

 

[rishabh_31ec]

Hi Anhnha,
I think you should follow the upper limit what Tom has suggested, just replace the Vsg3 in terms of Vsd3. Now for maximum gate voltage Vsd must be equal to Vdsat. In this way calculate Vdsat ( minimum Vsd ). In order to force M6 in saturation use output voltage swing specification and find Vdsat of M6 ( min Vsd for saturation ) and then take a safe value in order to keep it in saturation. I hope you are getting my words.....

 

[jony130]

Could you explain why we connect D and G of M3 together? I think it is to make sure that M3 will be in saturation.

No, this is not why we connect D and G of M3 together. M3 together with M4 form a current mirror circuit.
Please read this
https://forum.allaboutcircuits.com/showthread.php?p=678790#post678790 (post 33 and 39)

And could you explain how to force M6 to be in saturation?

You don't need to worry about M6, the negative feedback will take care of it and force M6 into saturation.
All you need is to close the negative feedback loop. Because this type of a amplifier will always work with negative feedback.

 

[anhnha]

Thank you, rishabh and jony.

@rishabh:
I still don't understand why should we replace Vsg3 by Vsd3(sat).
Let's consider two expressions talking about the same condition.
1. Vg1 <= VDD - Vsg3 + Vtn
2. Vg1 <= VDD - (Vdsat3 + Vtp) + Vtn
Is #2 is more complicated than #1?
For #1 to calculate the right hand side expression, we only need to find Vsg3.
For #2 to calculate the right hand side expression, we first need to calculate Vsg3. After that, we calculate Vsd3(sat) from Vsg3.
Vsd3(sat) = Vsg3 - Vtp
Finally we substitute that result into #2, we get the identical result as #1:
Vg1 <= VDD - (Vdsat3 + Vtp) + Vtn = VDD- (Vsg3 - Vtp + Vtp) + Vtn = VDD - Vsg3 + Vtn
Am I missing something?
I think #2 is preferred if we can calculate or measure Vsd3(sat) directly without Vsg3. However, I don't see that is possible.

In order to force M6 in saturation use output voltage swing specification and find Vdsat of M6 ( min Vsd for saturation ) and then take a safe value in order to keep it in saturation. I hope you are getting my words.....

In the case above, the author chose Vsg6 = Vsg4 = constant. So, the saturation voltage of M6 will also be fixed and equal to Vsg6 - Vtp.
To make sure that M6 is always in saturation, we need to control output voltage swing so that Vsd6 > Vsd6(sat) = Vsg6 - Vtp.
But this seems a bit complicated. How can we control output voltage swing?
vo = VO(dc component) + Vo(ac component)
Vo(ac component) = Av(voltage gain)*Vin.
To control voltage swing, which one should we change?
@jony:

You don't need to worry about M6, the negative feedback will take care of it and force M6 into saturation.
All you need is to close the negative feedback loop. Because this type of a amplifier will always work with negative feedback.

That seems interesting. Could you explain more or tell me some references?

 

[SIDDHARTHA HAZRA]

Hi anhnha,

The circuit is a two stage amplifier where the 1st stage is a single ended differential amplifier and the 2nd stage is a Common Source (PMOS input) amplifier.
Ideally, all the 7 MOSFETs should be in saturation. M1 & M2 can also be in sub-threshold to extract more gm.
The gain of the amplifier is A = A1*A2 = gm2 (ro2 || ro4) * gm6 (ro6 || ro7)

As this circuit is in open loop configuration, the MOSFETs in the same level have same bias. (What happens in closed loop can be discussed later)
Therefore, when I mean M2 I mean M1 as well and when I mean M4 I mean M3 as well.

Taking the 1st stage in to consideration:
1. The 1st stage has a NMOS diff pair. So the input common mode voltage should be high. So you will have a minimum value for the Input Common Mode Range (ICMR)
2. The minimum value can be derived from the saturation condition of the tail mosfet M5
M5 is in saturation if Vbias - Vth5 <= VDS5
Now, VDS5 = VS2 (the common source node) and VS2 = Vin - Vov2
Therefore, Vbias - Vth5 <= Vin - Vov2 or Vin >= Vbias - Vth5 + Vov2
3. So select a Vin such that the above equation is satisfied. (Keeping M2 in sub-threshold not only helps in increasing gm but also helps in operating the amplifier with a lower Vin as Vov2 is lower than in saturation)
4. Now approaching the saturation condition of M2 i.e the input differential pair.
This is restricted by the upper range of ICMR ( for PMOS input pair its just the reverse)
Here we will first assume Resistor load (similar to the 2nd picture in our post) then we will move to MOS load
(a) R Load:
With R load the Vout2 = VD2 = VDD - I*RD
For saturation of M2 ..... VD2 >= VG2 - Vth2 or Vout2 >= Vin(max) - Vth2 or VDD-I*RD >= Vin(max) - Vth2
So the maximum input common mode = Vin(max) <= VDD - I*R + Vth2 (Reducing the value of R will increase the maximum input voltage but will reduce gain)
(b) PMOS Load (in your 1st picture):
VD2 = VDD - VSG4
So the maximum input common mode = Vin(max) <= VDD - VSG4 + Vth2 (VSG4 can be reduced to increase the maximum input voltage)
5. Keeping the load M4 in saturation is easy. It shares a common VSG with M3 which is diode connected. As a differential amplifier is perfectly symmetrical so VD3 and VD4 are same, as if virtually shorted.
VD3 = VG3 = VG4 = VD4 so both M3 and M4 are inherently in saturation. You just need to control the VGS value to keep M2 and M1 in saturation as discussed in point 4.

This will ensure all the MOSFETs in the 1st stage to be in saturation.

Taking the 2nd stage in to consideration:
1. After the 1st stage is sized the 2nd stage PMOS (M6) is sized. The unit W/L of M6 is kept same as unit W/L of M4 for layout matching. In order to increase current we can increase the multipliers of M6, and change the effective W (keeping unit W/L fixed)
2. Once the size ratio is fixed the current ratio is also fixed we can size the M7. M7 will have same unit W/L as M5. To change the current multiplier can be varied (as mentioned in point 1)
3. As mentioned earlier VD4 = VG4 so VG6 = VG4. If the current is properly balanced then M6 and M7 will be in saturation automatically.
4. Proper balance of current:
(a) Say M5 has current I so M4 and M3 will have I/2 current
(b) If you want to burn 2I current in M6 then size of M6 will be 4 time of M4. i.e. W/L6 = Four times (W/L4) = 4 multiplier * (W/L4)
(c) M7 will be twice as big as M5 so in the last branch both the M7 & M6 are burning 2I current. So the current is balanced.

This will ensure all the MOSFETs M1 -- to -- M7 in saturation.


Hope this helps ......

 

[rishabh_31ec]

Hi, Anhnha;
You can design in any way but you have to take two points in consideration ( for low power small sized MOS );
(1) Vsg > -Vtp
(2) Vsd > - Vdsat
However I think #2 is more convenient as you know ICMR thus calculate in terms of Vg1.
I am explaining for the case when MOS length is less than 1u, under this situation Vdsat is not eqaul to overdrive voltage. Although Vdsat depends on Vov and in this case you are not able to calculate Vds directly. You can verify it in CADENCE.

 

[jony130]

In the case above, the author chose Vsg6 = Vsg4 = constant. So, the saturation voltage of M6 will also be fixed and equal to Vsg6 - Vtp.
To make sure that M6 is always in saturation, we need to control output voltage swing so that Vsd6 > Vsd6(sat) = Vsg6 - Vtp.
But this seems a bit complicated. How can we control output voltage swing?
vo = VO(dc component) + Vo(ac component)
Vo(ac component) = Av(voltage gain)*Vin.
To control voltage swing, which one should we change?

Do we need to worry about this in the firs place ? What will happen if M6 enter triode region?
The output voltage will be clipped. So M6 will limit the maximum positive output voltage.
And all amplifiers has specified output voltage swing. The maximum positive or negative peak output voltage that can be obtained without wave form clipping. So Vin_max = Vout_max/Av

@jony:
That seems interesting. Could you explain more or tell me some references?

Find Vout and Vsd6 for this circuit

 

[anhnha]

Hi.
Thank you very much for the detailed answer, SIDDHARTHA HAZRA.

2. The minimum value can be derived from the saturation condition of the tail mosfet M5
M5 is in saturation if Vbias - Vth5 <= VDS5
Now, VDS5 = VS2 (the common source node) and VS2 = Vin - Vov2
Therefore, Vbias - Vth5 <= Vin - Vov2 or Vin >= Vbias - Vth5 + Vov2

I am a bit confused about this.
Is Vov the overdrive voltage, Vov = Vgs- Vth?
If so, I think there is a small mistake here.
VS2 = Vin - Vgs2
Therefore, Vbias - Vth5 <= Vin - Vgs2 or Vin >= Vbias - Vth5 + Vgs2
This result is same as Razavi in posts #1 and #3.

3. So select a Vin such that the above equation is satisfied. (Keeping M2 in sub-threshold not only helps in increasing gm but also helps in operating the amplifier with a lower Vin as Vov2 is lower than in saturation)

Could you confirm this? To satisfy the equation above, we choose bias voltages as follows.
1. Vbias: choose Vbias as closer to Vth5 as possible. Also, that is also depend on the desired current. Id5 ≈ (Vbias - Vth)^2
2. Vin:
After completing step 1, we get Vbias fixed and so Id5.
Therefore, Vgs2 also fixed. It is calculate from the equation:
Id5/2 = k(Vgs2 - Vth2)^2
Solving this equation, we get Vgs2.
Finally, we get: Vin >= Vbias - Vth5 + Vgs2

4. Now approaching the saturation condition of M2 i.e the input differential pair.
This is restricted by the upper range of ICMR ( for PMOS input pair its just the reverse)
Here we will first assume Resistor load (similar to the 2nd picture in our post) then we will move to MOS load
(a) R Load:
With R load the Vout2 = VD2 = VDD - I*RD
For saturation of M2 ..... VD2 >= VG2 - Vth2 or Vout2 >= Vin(max) - Vth2 or VDD-I*RD >= Vin(max) - Vth2
So the maximum input common mode = Vin(max) <= VDD - I*R + Vth2 (Reducing the value of R will increase the maximum input voltage but will reduce gain)

Thanks, I got that. There is one problem. Is I = Id5/2 here?
I think it should be Id5/2.

(b) PMOS Load (in your 1st picture):
VD2 = VDD - VSG4
So the maximum input common mode = Vin(max) <= VDD - VSG4 + Vth2 (VSG4 can be reduced to increase the maximum input voltage)

I see you used the assumption that VSD4 = VSG4 and this will force M4 in saturation.
From here, we have VSG4 = VSG3 and calculated from the equation:
Id5/2 = k(VSG4 - Vth4)^2

5. Keeping the load M4 in saturation is easy. It shares a common VSG with M3 which is diode connected. As a differential amplifier is perfectly symmetrical so VD3 and VD4 are same, as if virtually shorted.
VD3 = VG3 = VG4 = VD4 so both M3 and M4 are inherently in saturation. You just need to control the VGS value to keep M2 and M1 in saturation as discussed in point 4.

Sorry, I don't get this. The lecture says that "M4 is the only transistor that cannot be forced into saturation by internal connections and external voltages."
And to solve that problem, the author derive the balance conditions and that force M4 into saturation.

Also, I don't think that the structure is perfectly symmetrical is M3 is a diode connected while M4 is not.

2. Once the size ratio is fixed the current ratio is also fixed we can size the M7. M7 will have same unit W/L as M5. To change the current multiplier can be varied (as mentioned in point 1)

I found that will violate balance conditions in the lecture.

4. Proper balance of current:
(a) Say M5 has current I so M4 and M3 will have I/2 current
(b) If you want to burn 2I current in M6 then size of M6 will be 4 time of M4. i.e. W/L6 = Four times (W/L4) = 4 multiplier * (W/L4)
(c) M7 will be twice as big as M5 so in the last branch both the M7 & M6 are burning 2I current. So the current is balanced.

I got it. However, this is a bit different from balance conditions given in the lecture.
The balance conditions:
(W/L6)/(W/L4) = 2(W/L7)/(W/L5)

 

[anhnha]

Thank you, Rishabh.

You can design in any way but you have to take two points in consideration ( for low power small sized MOS );
(1) Vsg > -Vtp
(2) Vsd > - Vdsat

Yes, I understand that.

However I think #2 is more convenient as you know ICMR thus calculate in terms of Vg1.

Could you explain a bit more?

I am explaining for the case when MOS length is less than 1u, under this situation Vdsat is not eqaul to overdrive voltage. Although Vdsat depends on Vov and in this case you are not able to calculate Vds directly. You can verify it in CADENCE.

Well, it is strange. I will simulate it and posted the result.

- - - Updated - - -

Thank you, Jony.

Do we need to worry about this in the firs place ? What will happen if M6 enter triode region?
The output voltage will be clipped. So M6 will limit the maximum positive output voltage.
And all amplifiers has specified output voltage swing. The maximum positive or negative peak output voltage that can be obtained without wave form clipping. So Vin_max = Vout_max/Av

That means we have to specify the maximum output voltage first?

Find Vout and Vsd6 for this circuit

Av = gm1 (ro1 || ro3) * gm6 (ro6 || ro7)
Acm: common mode gain.
Vout = (1+ Vout)/2 * Acm + (1- Vout)/2 * Av
Well, I don't know how to calculate it.
Could you explain a bit? How to know Acm?

P.S. I think in this case, we consider the op-amp ideal. And so, Acm = 0.
Vout = (1- Vout)/2 * Av
or Vout( 1 + Av/2) = Av/2
Vout = Av / (2 + Av)
If Av is very large, Vout = 1V.
Vsd6 = Vs - Vd = 5 - 1 = 4V.

 

[SIDDHARTHA HAZRA]

hi anhnha,

1) You are write about he first one it will be VGS2 not Vov2

2) Regarding the Vbias: Yes after the 1st step we get the current and the Vbias fixed. But the VGS2 is in our hand. We can size the M2 such that VGS2 just less than Vth, which will operate M2 in sub-threshold.
If we decrease the W/L the VGS2 will start increasing and it will cross VTH2. At this time M2 will operate in saturation. So its out choice how to size and operate M2

3) Ya I meant it in general .... of course here it is Id5/2

4) Its not an assumption .... Its a fact that VDS3 = VSG3 = VSG4 = VDS4 ..... this because a differential amplifier is perfectly symmetrical

5) By symmetry I meant equal current distribution. Yes I agree with the author that M4 is hard to keep in saturation if I had a simple CS amplifier or in a double ended differential amplifier ..... so we go for Common mode feedback (CMFB) in case of double ended output .... But in single ended its not a problem at all .... You can design one and see in Cadence ... Its is hard to explain here but the diode connected MOS, M3, actually is providing a CMFB. ....
It is really hard to prove this point .... so just test and see that VDS3 = VDS4 in open loop ..... (as I said earlier in closed loop VDS4 is not equal to VDS3 there the design approach will be slightly different)

6) I could not get what will " violate balance condition in lecture " ???

7) This is correct... what I said I exactly the same .... If you use 2*Id5 in the second arm them W/L6 will be twice of W/L4 and W/L7 = W/L5 ..... that is what the equation in the lecture says .... but say if you need 5 time current then will it still not be in balanced condition ???? Of course it will be if you size them correctly .... for 5*Id5 the W/L6 = 10W/L4 and W/L7 = 5*W/L5 so this also gives us the same equation as in the lecture ...... thats what I meant

Hope this will help ...

 

[anhnha]

Thank you, SIDDHARTHA HAZRA.

2) Regarding the Vbias: Yes after the 1st step we get the current and the Vbias fixed. But the VGS2 is in our hand. We can size the M2 such that VGS2 just less than Vth, which will operate M2 in sub-threshold.
If we decrease the W/L the VGS2 will start increasing and it will cross VTH2. At this time M2 will operate in saturation. So its out choice how to size and operate M2

Ya, I see.
Id5/2 = k W/L (Vgs2- Vth2)
Id5 and Vth2 are constants.
If we want it to operate in sub-threshold, choose Vgs2 just below Vth2. From that equation, we can find out the W/L ratio.
If we want it to operate in saturation, choose Vgs2 just above Vth2. From that equation, we can find out the W/L ratio.

5) By symmetry I meant equal current distribution. Yes I agree with the author that M4 is hard to keep in saturation if I had a simple CS amplifier or in a double ended differential amplifier ..... so we go for Common mode feedback (CMFB) in case of double ended output .... But in single ended its not a problem at all .... You can design one and see in Cadence ... Its is hard to explain here but the diode connected MOS, M3, actually is providing a CMFB. ....
It is really hard to prove this point .... so just test and see that VDS3 = VDS4 in open loop ..... (as I said earlier in closed loop VDS4 is not equal to VDS3 there the design approach will be slightly different)

I think I get the point.
1. Ids3 = Ids4 = Id5/2 = constant.
2. W/L3 = W/L4
3. Vsg3 = Vsg4
From that Vsd3 should be equal to Vsd4.
Also, because M3 is in saturation, M4 should also be in saturation.
Could you explain why VDS4 is not equal to VDS3 in closed loop?

7) This is correct... what I said I exactly the same .... If you use 2*Id5 in the second arm them W/L6 will be twice of W/L4 and W/L7 = W/L5 ..... that is what the equation in the lecture says .... but say if you need 5 time current then will it still not be in balanced condition ???? Of course it will be if you size them correctly .... for 5*Id5 the W/L6 = 10W/L4 and W/L7 = 5*W/L5 so this also gives us the same equation as in the lecture ...... thats what I meant

I see it now. :-D
W/L6 = 2* W/L4
This means that I6 = 2I4 = 2*Id5/2 = Id5
W/L7 = W/L5 that means I7 = I5

 

[SIDDHARTHA HAZRA]

Could you explain why VDS4 is not equal to VDS3 in closed loop?

Consider only the 1st stage (i.e. a single stage op-amp). Now if we connect it in a buffer configuration then we must short Vout and M2 gate. As in a buffer the Vout = Vin so the Vout = VD4 = Vin which is not equal to VD3.
Now if we have a high Vin say close to VDD then M4 might not get sufficient VDS and may be pushed into linear region even if M3 is in saturation. Here, the loop controls the voltage of every high impedance node, like that of the Vout.

Hope this helps ....

 

[jony130]

Thank you, Jony.
That means we have to specify the maximum output voltage first?

P.S. I think in this case, we consider the op-amp ideal. And so, Acm = 0.
Vout = (1- Vout)/2 * Av
or Vout( 1 + Av/2) = Av/2
Vout = Av / (2 + Av)
If Av is very large, Vout = 1V.
Vsd6 = Vs - Vd = 5 - 1 = 4V.

You as a IC designer need to design a circuit that give us as much output voltage swing
as possible. Also notice that as long as your amp will work in closed loop and and in linear region M6 will stay in saturation region.