Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Biasing the transistors in the output stage of the op-amp

Status
Not open for further replies.

Junus2012

Advanced Member level 5
Advanced Member level 5
Joined
Jan 9, 2012
Messages
1,552
Helped
47
Reputation
98
Reaction score
53
Trophy points
1,328
Location
Italy
Visit site
Activity points
15,235
Hello all,

In the small signal condition, transistors M5-M10 of the folded cascoded amplifier shwon below have a current of Ib, but at the time of slewing they will handle a current of 2Ib

Questions:

1. Should I size these transistors according to Ib or 2Ib ?, do we still need these transistors to be in saturation in the time of slewing and why ?
2. Biasing voltage Vbp2 should be designed according to 2Ib or Ib

Thank you very much

Regards

folded.PNG
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top