Biasing the cascode pair

[archiees]

hi,
I came across this circuit while studying low nose differential amplifiers. The cascode JFETs which are connected has their Gate tied together to the source of the input FETs. I don't understand how this biasing works.
The JFETs have the VGS(off) ~ -0.5. There is no way all the FETs are biased in their active region.
DOn't we want to keep all the 4 JFETs in the active region? I have made circuits in which i bias the cascode transistors by connecting their gate to the VCC via a resistor.
Is it some low noise technique to have this configuration...are there any advantages?
Please help?

 

[Humungus]

Actually they can all be saturated. They are depletion JFETS so that they can operate with a negative Vgs.

 

[archiees]

Humumgus,
I was implying do we have to bias such that VDS > VGS- Vth, to keep JFETs in the constant current region.

 

[Humungus]

Take a careful look at the architecture. Even if the Vgs is negative or zero, there is room to have Vds of all transistors positive. The aproximation Vds>Vgs-Vth is only valid for deep strong inversion. Actually, once Vgs approaches Vth, some Vt=K.T/q are only needed as Vds to get a constant Ids. Assuming the tail current works in saturation, the size of the cascode transistors can be designed to get the differential pair into saturation and then everything works fine.

 

[nxing]

When the common-mode voltage of the input increase, the gate of Q1 & Q2 will increase accordingly to maintain them in the saturation region.

 

[archiees]

Sorry for being a real pain guys. Still i don't get one thing.
Ok, let me tell you how i am trying to bias the design.
Just take resistor values to be Rd1 and Rd2.

VG3=VG4=0 volts.
I want the Q3 and Q4 to be biased at VGS = -0.6 and VDS = 3.5 volts. (IDS ~ 10 mAmps for these bias values)
So we assume the VS3=VS4=0.6 volts.
Now, the VD3 and VD4 has to be driven to 4.1 volts. (to keep VDS = 3.5 volts).
Checking the Q1,
VGS1 = 0.6 - 4.1 = --3.5, but the VGS(off) ~ - 2 volts. Here VGS is less than Vth so how this thing will work.
This is where i stumble. How to proceed further and how to select the Drain resistors?