Biasing CMOS analog design

Status
Not open for further replies.
I would create a pmos "flavour" from the left most branch
 

Hi,

May i know the supply voltage ... and whats your output voltage?

And use the upper Pmos current source bias or use seperate leg if you want precise bias voltage.. It depends on you...

Thanks
 

kenambo said:
Hi,

May i know the supply voltage ... and whats your output voltage?

And use the upper Pmos current source bias or use seperate leg if you want precise bias voltage.. It depends on you...

Thanks
Click to expand...

actually my qsn states that i need a high CMRR and high swing(2.2v)
supply is 3.3v... so a diode connected bias wont work
 

sry forgot to mention cant use resistors...
as of now i have done using a diode connected pmos(with a different W/L) and gave its gate volatge...
but the matching isnt perfect
 

chiragjain146 said:
sry forgot to mention cant use resistors...
as of now i have done using a diode connected pmos
Click to expand...

Instead, try and use a (small) pmos with its gate connected to GND or to one of the n-bias voltages. Or an nmos with its gate connected to the upper p-bias voltage, or to VDD.
 

chiragjain146 said:
i need a high CMRR and high swing(2.2v)
supply is 3.3v... so a diode connected bias wont work
Click to expand...

Hi Chirag,
As u need good output swing, you can go with Low voltage Cascode Current Mirror circuit mention in Razavi.
One more point : In your circuit How You are generating gate bias for your PMOS tail current mirrors. It looks like your PMOS (diode connected 3rd branch) is off.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…