Biasing Circuit and power strapping

[dream_taker]

Hi,

Anyone have lecture notes or document regarding Biasing circuits. Also if anyone can infom me regarding power strapping. How to calculate the width of Vdd/Vss lines in the layout.

 

[Vamsi Mocherla]

Please refer to ECE569 Analog IC course in High Speed CMOS IC LAB, POSTECH. Do a google search for the link. I am sure you will find good info.

Coming to the widths of the power lines, it is quite simple. Calculate how much current VDD and VSS supply or sink. Then for every 1 mA current, the width shall be 1um in many processes. Check your process files for that.

I hope this helps

 

[dream_taker]

If we have a Digital Block or Analog block and I am composing the chip, then how to do the power strapping to the Vdd/Vss lines from each block to the pads running around the chip.

Maybe Digital block is having only one metal (metal-4 say) but there is a possibility of using M3.

 

[Vamsi Mocherla]

Well, you can do it in two ways.
1. you can run a ring across all the circuits and then connect all the small circuits to it.

2. You can put alternating fingers of VDD and VSS parallel using a higher level metal. Then you can place all your circuits in it which obviously consist of lower layer metals.
Then you can join all the VDD on one end and VSS on the other end.