Biasing a Single Stage Cascode Amplifier

Hi,

First of all, it looks like one transistor from current mirror is missing from your design (M5 from the picture attached).


Then, you are trying to bias PMOS cascode while generating the bias voltage using NMOS. You should use the same type of transistors to create bias to achieve better temperature and process variation robustness. You can try to use a self-biased current mirror, adjusting the resistor size and W/L of the PMOS devices to generate bias as shown below:

Hopefully, that helps.

What I notice is your differential transistors are a 'long-tail pair'.

M9 is the tail resistance configured so that an unchanging sum current passes through the two columns (left and right).

When one column conducts more, automatically it forces the other column to conduct less.
When one column conducts less, it allows the other column to conduct more.

The action is governed by your signal (in other words, changing bias voltage).
The goal is to operate all mosfets (bias them) in a range so that you see this 'give-and-take' action between the left and right columns.

You must test whether M9 is admitting sufficient current so that all mosfets operate at: a) their proper voltage thresholds, and b) are affected by your incoming signal so they respond.

It will help in the development stage, if you put a current source in place of M9. Change its current value until it adjusts itself so that it pulls the correct sum current through your system. At that point it should tell you the correct negative voltage at the negative supply rail. It is not necessarily a symmetrical amplitude as your positive rail.