Biasing a cascode stage technique

Hi,
I am trying to find the right method to Bias a cascode amplifier with cascode PMOS load. I have read Razavi CMOS chapter 9 of single stage opamp and Sansen book to find only general theoretical answers and not practical ones... also search this forum as well.

I have set Vbat=2V, Ibat~1mA. my technology is tsmc130nm with Vth~400mV.

I've tried 2 methods -
1. "cadence monkey" - just play with each transistor until it is in saturation region and then continue to the next one
2. assuming Vod on all of the transistors and then using gmoverid to calculate W while L is fixed on 130nm

both methods give me hard time. below is my circuit after implement some calculations -


does M3 determine the circuit Ids ? or is it the configuration of all the 4 together ?
does I need Vds to be small on every transistor from top to bottom in order to reach enough Vd on M1 (the amplifier device) ?

appreciate your help

daniel442 said:

does M3 determine the circuit Ids ? or is it the configuration of all the 4 together ?

Click to expand...

There are two current sources in series --> M3 and your main amplifier (M1). When two current sources fight, the output voltage common mode is undefined.

does I need Vds to be small on every transistor from top to bottom in order to reach enough Vd on M1 (the amplifier device) ?

Click to expand...

I am not exactly sure what you mean, but here goes:
Vout,max=Vdd - sum{overdrive voltages of top devices)
Vout,min= sum{over-drive voltages of bottom devices}
So you minimize overdrives of all devices to get as much swing as possible.

No monkey based approach will not work. There is some biasing networks described in Razavi's text book. Use them.

Thanks for the answer vive, but before using any Bias network, I would like to use ideal voltage sources and determine the bias voltage. I cannot seems to pass that point - any tips?

Yes.. You can start with voltage source to bias the cascodes.

A complete circuit would be as attached.

thank you again vive for the answer, but maybe I will make myself more clear - I am in a more beginner stage right now. I cannot seem to calculate the right Bias voltage (e.g Vg) for each transistor in order for it to be in saturation and receive high gain (high Rout from M2,M0,M3). it seems that I do not know how to calculate the desired Vg for each transistor. I've tried several calculations to determine Vb1,Vb2,Vb3 but it seems that I still don't have enough headroom from the 2V, is that make sense ? can anyone help me with the calculation to determine the Bias voltages ? (after I will know the voltage, I will build a bias network...)

I use a different simulator than Cadence, and I find its mosfet model doesn't operate the way I expect it to. Often it does not turn on until I apply extremes of bias voltage.

It makes me gravitate to BJT instead. Their response is much more predictable.
Advantages:

* It's a helpful indicator for me to see what amount of bias current is flowing. It tells me I've drawn the circuit so it provides a return path for transistor current.

* It tells me proper volt levels are applied to the transistor so that it should operate. These voltages may depend on the state of neighboring devices. So I get a clue to operation of those devices too.

Your schematic has a combination of mosfets in a totem arrangement and mosfets in a half-bridge. It's hard to be certain which device prevents current flow, and which device is improperly biased.

Also your load appears to be a capacitor. While the project is in a development stage, try attaching a resistive load since that is easier to work with. A capacitor blocks DC when it becomes charged. Then no current flows regardless whether your mosfets are biased properly.