Bias voltage variation with respect to process variation

[bharatsmile2007]

Hi,

I am designing a folded cascode opamp with pmos diff pair.
In this i have a four bias pins.
My supply voltages are 3.3(typ), 3.6(ff), 3.0(ss)
My question is
1. what is the bias voltage variation with respect to process variation(typ, ff, ss)?
2. write now i have bias voltages for typical are 2.62v, 1.96v, 1.14v, 0.707v. But the variation in fast corner are 2.92v, 2.26v, 1.44v, 0.84v
If you observe clearly the variation is about 0.3v for first three, where as the bias voltage variation is about 0.17v. Is this ok or we need to adjust to 0.3v variation?

Thanks in advance.

 

[love_analog]

You need to post a schematic with a clear note on all the bias lines. It is very difficult to follow what you are saying.
In general you want Vds>Vdsat+100mV (at least) if thats what you are looking for.