[SOLVED] Bias strategy for multiple analog blocks sharing a same current reference

In the design of an analog system (e.g. filter) with multiple blocks (e.g. OTAs), I am in doubt about what is the best bias strategy. If all blocks were equal, one could design the current reference tailored specifically to that block. With multiple blocks, however, should all of them use currents that are multiples of a same current source (option 1 in the image attached)? As far as I know, while reducing mismatch problems (explanation in Baker's book), this would impose a constraint in the design of each block (discrete choice of currents and the reference current would have to be known beforehand).

On the other hand, if we could change the lengths (option 2 in the image) or widths (option 3) of the mirror transistors, mismatch would probably be worse (would it?) but there would be continuous choice of current for each block.

Do you guys can provide me any insight about this topic? How this is usually done in practice?

towalker said:

... if we could change the lengths (option 2 in the image) or widths (option 3) of the mirror transistors, mismatch would probably be worse (would it?) but there would be continuous choice of current for each block.

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I think the best way is to use option 3, but always use the same transistor and just change the multiplier (or number of fingers, perhaps). This would of course imply that the original Vbias generator uses the smallest current.

The mismatch shouldn't be (much) worse than from option 1 , because the current generating vbias transistors are remote from each other in both cases, not adjacent. Good matching needs adjacent transistors.

Here is another methodology: using distributed bias currents instead of bias voltage. In this case the bias currents can be generated in a common block, by this could have better matching because they are much closer. Also, their crosstalk sensitivity could be (a bit) lower. Disadvantage is more space demand.

For bias current vs. bias voltage distribution, you might check this discussion.

It is important the transistors in a current mirror have the same size. So if the PMOS transistor in the beta multiplier is 10/0.5um, then you must also use these transistor sizes in the PMOS in your OTA that you are biasing with this current. If you want to increase the current (e.g. with a factor 5), then you just use 5 transistors in parallel.
If you use a ratio of 1:100, then you will easily have some mismatch. But in case of biasing that mismatch is often not problematic.
So, you never use a different Length, but always a different Width. You adjust these widths using the multiplier and keep all transistors the same size.

Thank you for your replies. As far as I understood, it seems a consensus that one should always keep the current at the blocks as integer multiples of the original current reference. And this is to be achieved by using transistor multipliers (or fingers).

If block A were to be designed by a team and block B by another, this would imply that both teams would have to agree in a common current reference value BEFORE starting to design the blocks (because their current options will be constrained to n*iref, where n is an integer). Is that right?

Erikl, I read the discussion you referred to in your post, but I'm afraid I'm not familiar with how this alternative approach is performed. Do you know any other material that could provide me a better understanding of that?

Thank you

towalker said:

Erikl, I read the discussion you referred to in your post, but I'm afraid I'm not familiar with how this alternative approach is performed. Do you know any other material that could provide me a better understanding of that?

Click to expand...

Unfortunately I don't have a paper on that, sorry. I worked on a mixed analog chip design with a team of colleagues, each of us being responsible for different analog blocks. It was decided that each block would receive a sink input current of 100nA from a common current generator block, generating its output currents from a bandgap controlled, rather (P)VT independent master current source.

The output currents were delivered via an analog bus 100nA<10:1>, i.e. 10 sinking current sources with 100nA each. Every analog block designer could use one of these sink currents to use as his own sinking bias current source, or mirror it to a VDD referred (perhaps multiplied) sourcing current source.

Worked well, with very good matching and VT-independence.

erikl said:

Unfortunately I don't have a paper on that, sorry. I worked on a mixed analog chip design with a team of colleagues, each of us being responsible for different analog blocks. It was decided that each block would receive a sink input current of 100nA from a common current generator block, generating its output currents from a bandgap controlled, rather (P)VT independent master current source.

The output currents were delivered via an analog bus 100nA<10:1>, i.e. 10 sinking current sources with 100nA each. Every analog block designer could use one of these sink currents to use as his own sinking bias current source, or mirror it to a VDD referred (perhaps multiplied) sourcing current source.

Worked well, with very good matching and VT-independence.

Click to expand...

Thank you for sharing your experience. I am glad that such level of cooperation exists and thank you for that.

In the attached image in this reply, I tried to illustrate my understanding of the concept of distributing current sources instead of voltages you referred to. Is it right?

You mentioned that your project team chose a sinking bias current (as illustrated on the image). As a consequence, I suppose the NMOS transistors in the blocks are then biased by a second mirror generated within each block.

In cases where there are folded cascodes within the blocks, all bias voltages would have to be generated internally in each block from the delivered current. Is that also right?

towalker said:

In the attached image in this reply, I tried to illustrate my understanding of the concept of distributing current sources instead of voltages you referred to. Is it right?

You mentioned that your project team chose a sinking bias current (as illustrated on the image). As a consequence, I suppose the NMOS transistors in the blocks are then biased by a second mirror generated within each block.

In cases where there are folded cascodes within the blocks, all bias voltages would have to be generated internally in each block from the delivered current. Is that also right?

Click to expand...

You're absolutely right, in every of your paragraphs above, and your image.

In the end, both sinking and sourcing constant currents (CC) had been provided, as well as CTAT and PTAT type CCs. There were a lot of various analog blocks ...

Either voltage or current mode bias distribution has its
plusses and minuses. With voltage mode you worry about
ground offsets and cross-chip VT gradients. With current
mode, especially very low currents (hence high net
impedance) you worry about signal coupling from digital
aggressors and HF power supply noise. Which of these
is worse, depends on your architecture, how much you
get to decide about grounding scheme & integrity, how
much you can dictate keep-out / keep-away of noisy
signals, how big the chip and how DC- and AC-variable
one ground X,Y point can be relative to another. And
in the end it's probably some sort of hybrid - like, you
may be fed a bias current at the block level but almost
surely there is voltage mode "distribution" intra-block
(VBN, VCN, VBP, VCP or some such).

Along with the bottom-up thinking you probably want to
take some time with the floor plan view and decide how
to weight these concerns.

I think you'll end up at current-mode, globally, bit if you
had all the analog stuff crammed into one nice protected
corner then a common voltage set might be simpler and
good.

dick_freebird said:

With current mode, especially very low currents (hence high net impedance) you worry about signal coupling from digital aggressors and HF power supply noise.

Click to expand...

Wouldn't the net impedance be about comparable between both methods?

In contrast to the bias voltage distribution, in fact with a relatively low-impedance (diode-connected transistor) generator but just a gate load, in case of bias current distribution a high-impedance generator, but a relatively low-impedance source tail load or a diode-connected transistor load instead, i.e. a comparable total net impedance for both - at least in principle.

Once again, thank you all for sharing. I will ask a follow up question which is directly applied to Gm-C filters. So, if you think it should (or deserves to) be placed in a new thread, please tell me.

In Gm-C filter design, the element that is usually tuned to keep the right filter frequency despite PVT variations is the gm of the OTA. Its gm is proportional to square root of Ibias when in saturation, so one could directly tune it by adjusting the bias current. Reading several papers on the topic, one doubt still remains: can all OTAs be tuned together (same Ibias)?

The figure attached shows a filter topology example using biquads. Changing gm of one OTA would affect the freq. of its biquad, but is changing ALL gms at the same time an appropriate tuning strategy?

Another question would be: what are good topologies to implement a current reference with a vcontrol terminal?

P.S: For simplification reasons, I am considering only manual tuning for this discussion

Tuning Gm-C filters: with different OTAs, can we use the same tuning circuit?

Hey guys,

In addition to what I have said in the last post, I have realized that in the papers I've seen so far, all OTAs are indeed tuned together (same Vbias). Some of them mention they use the same OTA blocks. Is making all OTAs equal a necessary condition for using the same tuning circuit reliably?

Thank you all,