Depending on accuracy rollup required you may need two trims, as TC moves VOUT and that must be set, last.
In CMOS your best bet is shunt switches across resistor segments. Your present error-band divided by required accuracy "bin" width, log2, gives #bits (must add in the TC "pull" on VOUT to the range).
Give yourself a trim-bit interface that lets you "run the codes, bump the temp, run the codes, pick the right one". This is big data volume at wafer level but the code-pick demands no intelligence, only bookkeeping.