BGR Trimming

[Mounikap]

Hello All,

I am designing the BGR which gives the output reference voltage of 600mv. In TT state the output reference voltage is 600mv but in FF state the output reference voltage is 545.8mv and in SS state the output reference voltage is 639.4mv. So to get 600mv across PVT variations in all (TT, FF, SS states) I would like to use the trimming method in BGR circuit. Can anyone please guide me how can i design trimming for the BGR circuit ?

 

[sidun.av]

Hi @Mounikap
In my opinion, your output voltage variation is quite high. Probably, it worth analysing currents/voltages across PVT as well as performing sensitivity analysis to find the device impacting the output voltage variation.
In terms of trimming, it's hard to suggest without looking at your schematic, so please attach one. Most frequently, we do trim output voltage through the output resistor adjustment (i.e. for Banba bandgap architecture). We have to have a closer look at your schematic to conclude what's the best solution.

 

[Mounikap]

Thank you so much for your reply.

Yes the output voltage variation is high. The input offset of op-amp is also less. But i don't know how to reduce the variation of the BGR across PVT.

I have used the OP-AMP based BGR. To generate the current i have used the beta multiplier. Here i am attaching the schematic of BGR. Please check once.

 

[sidun.av]

Your output voltage variation can be impacted by:
1. Gain variation of your opamp (which will impact the precision of your output voltage which is your bias for a current mirror)
2. Channel-length modulation effect of your current mirror (highlighted in green on my screenshot) -> increase length and width proportionally;
3. It also worth checking whether your variation is caused by moving along the curvature of the output voltage or it's simply an offset and the PVT dependency shape doesn't change.

Regarding the output voltage trimming, I recommend trimming the output resistor (highlighted in yellow).
Hopefully, that helps.

 

[dick_freebird]

Depending on accuracy rollup required you may need two trims, as TC moves VOUT and that must be set, last.

In CMOS your best bet is shunt switches across resistor segments. Your present error-band divided by required accuracy "bin" width, log2, gives #bits (must add in the TC "pull" on VOUT to the range).

Give yourself a trim-bit interface that lets you "run the codes, bump the temp, run the codes, pick the right one". This is big data volume at wafer level but the code-pick demands no intelligence, only bookkeeping.